VHDL-200x

Since the publication of the first IEEE standard in 1987 several revised versions have appeared. The first, in 1993, had the most extensive changes. VHDL 2000 Edition introduced protected types and VHDL-2002 contains mainly minor changes. VHDL-200x is the name commonly given to the proposed next version of VHDL. As with the earlier revisions, this doesn’t radically alter the language, but it does provide a wider set of modifications than previously.

A draft of the proposed revision (version 4.0) was delivered by Accellera to the IEEE in 2008, where balloting will take place. If balloting is completed in 2008, then the standard would be known as IEEE Std. 1076-2008.

Support for some of these changes has begun to appear in simulators. Widespread support is only expected once the IEEE standard is published, and tool vendors consider that there is sufficient demand for the changes from their customers.

Summary of Changes to VHDL in VHDL-200x

The changes to VHDL that are proposed in VHDL-200x fall broadly into these categories:

Existing separate VHDL standards are incorporated into the LRM.
VHDL is enhanced significantly in some areas.
Changes that make VHDL (slightly) less cumbersome to use.
A number of smaller enhancements.

VHDL-200x Features

This is not an exhaustive list of all the proposed changes to VHDL, but is intended to give an overview of what is proposed.

Incorporation of existing VHDL standards

The STD_LOGIC_1164, MATH_REAL, MATH_COMPLEX, NUMERIC_BIT and NUMERIC_STD packages are incorporated into the VHDL standard.
The functionality of Synopsys’s STD_LOGIC_TEXTIO package is added to TEXTIO. IEEE.STD_LOGIC_TEXTIO exists for backwards compatibility, but is empty.
The VHPI standard (1076c-2007) has been incorporated

Significant Enhancements

PSL (Property Specification Language – see The Designer's Guide to PSL) is incorporated into VHDL. This means that PSL statements no longer need to be comments.
Packages and subprograms may now have generics. This makes it easier to write reusable code.
Generics may be constants, types, subprogram declarations, or package declarations.
New synthesizable fixed and floating point arithmetic packages are added: MATH_UTILITY_PKG, FIXED_GENERIC_PKG and FIXED_PKG for fixed-point and FLOAT_GENERIC_PKG and FLOAT_PKG for floating-point.

Features that make VHDL easier to use

Condition operator, ?? - converts bit and std_logic to boolean.
Implicit application of the condition operator: expressions of type bit and std_logic are interpreted as boolean, for example in if statements.
Bit string literals are enhanced: they may have a width; they may be declared as signed or unsigned, for example 10UX"3fff" or decimal, for example 8D"10".
External names, that is hierarchical names, are introduced.
Aggregates allow a vector, e.g. ('0', V) where V is a vector
Conditional (when..else) amd selected (select..with) are allowed as sequential statements.
Extensions to generate: if..elsif..else and case..generate
Context declarations – allow grouping of sets of library and use clauses. Standard synthesis context decalarations for bit and std_logic are added.
Two new synthesizable arithmetic packages are added: NUMERIC_STD_UNSIGNED and NUMERIC_STD_SIGNED. These are similar to Synopsys’s STD_LOGIC_UNSIGNED and STD_LOGIC_SIGNED packages.

Miscellaneous Enhancements

New standard functions: minimum, maximum and to_string are defined for scalar and array types; to_bstring, to_binarystring, to_ostring, to_octalstring, to_hstring, and to_hexstring for arrays.
Function rising_edge is defined for type boolean.
Arrays and records may contain unconstrained elements.
These new array types are added: boolean_vector, integer_vector, real_vector, and time_vector.
Unary reduction operators, for example and V ands together the elements of the vector V.
New procedure flush for files
“Matching” equality/inequality operators: ?=, ?/=, ?<, ?<=, ?>, ?>= ('-' is treated as a wildcard).
“Matching” case statement, case?
Implicity sensitivity list: process(all)
force and release for signals.
/* */ block comments.
'INSTANCE_NAME etc. extended for package and subprogram instantiation.
New TEXTIO procedures SREAD and SWRITE.
New standard environment package, ENV that includes procedures stop and finish and function resolution_limit.
IP encryption directives (protect) are added.