Global training solutions for engineers creating the world's electronics
SystemVerilog & UVM Training
In line with the demands for finely tuned training programs for application to both design and verification contexts, Doulos has created an enhanced portfolio:
This is a one-stop solution addressing the needs of both design and verification groups. It includes objective and up-to-date commentary on the three best-known published verification methodology approaches, and teaches key SystemVerilog language features that support them.
The key to its success (and that of our clients' subsequent SystemVerilog-based designs) is our careful handling of what many consider a difficult topic, class-based SystemVerilog verification. This is a critical part of the SystemVerilog learning path. If it isn't taught well, engineers will take much longer to put what they've learned into practice, and find SystemVerilog much harder than it actually is. Doulos has leveraged years of experience in teaching object-oriented verification concepts to make these challenging topics easier to learn for engineers from a wide variety of backgrounds. This makes the Doulos class the ideal preparation for subsequent adoption of a sophisticated verification methodology such as UVM, OVM or VMM (which are covered in our UVM, OVM and VMM Adopter classes). More >>
The difference between Comprehensive SystemVerilog and SystemVerilog for Verification Specialists is that Comprehensive SystemVerilog includes an extra day of material near the front end of the course on the general programming language features of SystemVerilog and features used for hardware design, whereas SystemVerilog for Verification Specialists focusses exclusively on verification. Comprehensive SystemVerilog is more suited to engineers with an HDL background, whereas SystemVerilog for Verification Specialists is more suited to engineers who already have a good grasp of a language such as C++, e, or Vera.
These classes provide a quick-start, practical introduction to the respective approaches to SystemVerilog verification methodology. They can be presented as a 2-3 day class giving hands-on experience of the chosen methodology, or as a ½ to 1-day overview to introduce the key ideas and benefits. They are designed for use within the context of Doulos team-based SystemVerilog verification training (see Modular SystemVerilog below) but can also be used stand-alone, and packaged with flexible project support options. Supplemental tool training with specific tools can also be provided in co-operation with the leading vendors. Use the links below to find out more about how Doulos can assist you with UVM, OVM or VMM adoption.
UVM Adoption & Adopter Class
OVM Adoption & Adopter Class
VMM Adoption & Adopter Class
Unique team-training packages for each unique team
Nearly 20 years experience of migrating whole teams and organisations to new methods has taught Doulos that the best outcomes are experienced when training programs are carefully tuned to the client's context. Off-the-shelf training is rarely sufficient.
Significant factors include the training objectives, the customer's tool flow, the application domain, the extent of the methodology migration required and the pre-existing know-how across the customer team.
Doulos addresses all in-house and team-based training as a potentially unique training program - no assumption is made as to the scope, duration and content of the training required. Instead, a Doulos SystemVerilog expert draws up a specific training program and proposal based on a direct interaction with a client's technical lead, and the Modular SystemVerilog syllabus and materials. More >>
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