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Xilinx - Vivado HLS ONLINE

Also known as C-based Design: High-Level Synthesis with the Vivado HLx Tool by Xilinx.

PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE.

It covers the same scope and content as a scheduled face-to face class and delivers comparable learning outcomes. Daily sessions comprise 4-6 hours of class contact time.

Course Description

The course provides a thorough introduction to Vivado® HLS (high-level synthesis). It covers:

  • Synthesis strategies
  • Features
  • Improving throughput
  • Area
  • Interface creation
  • Latency
  • Testbench coding
  • Coding tips.

You will learn how to utilize Vivado HLS to optimize code for high-speed performance in an embedded environment and download for in-circuit validation.

This training also provides an essential background for developing Software Defined SoCs (find out more about Doulos SDSoC Adopter Training).

New content (2020) on:

  • Vitis™ HLS tool
  • RTL Verification, IP packaging, and design analysis
  • All labs now support the Zynq® UltraScale+™
    ZCU104 board
Training Duration

4 sessions (Details » )

Who Should Attend?

Software and hardware engineers looking to utilize high-level synthesis.

Engineers looking to develop Software Defined SoCs (see SDSoC Adopter Training).

  • C, C++ or System C knowledge
Skills Gained

After completing this comprehensive training, you will know how to:

  • Enhance productivity using Vivado HLS (high-level synthesis)
  • Describe the high-level synthesis flow
  • Use Vivado HLS for a first project
  • Identify the importance of the testbench
  • Use directives to improve performance and area and select RTL interfaces
  • Identify common coding pitfalls as well as methods for improving code for RTL/hardware
  • Perform system-level integration of blocks generated by Vivado HLS
  • Describe how to use OpenCV functions in the Vivado HLS tool
Course Outline
Sessions 1 & 2
  • Introduction to High-Level Synthesis
    Overview of the High-level Synthesis (HLS), Vivado HLS tool flow,
    and the verification advantage. {Lecture}
  • Vivado HLS Tool Flow
    Explore the basics of high-level synthesis and the Vivado HLS
    tool. {Lecture, Demo, Lab}
  • Design Exploration with Directives
    Explore different optimization techniques that can improve the
    design performance. {Lecture}
  • Vivado HLS Tool Command Line Interface
    Describes the Vivado HLS tool flow in command prompt mode.
    {Lecture, Lab}
  • Introduction to HLS UltraFast Design Methodology
    Introduces the methodology guidelines covered in this course and
    the HLS UltraFast Design Methodology steps. {Lecture}
  • Introduction to I/O Interfaces
    Explains interfaces such as block-level and port-level protocols
    abstracted by the Vivado HLS tool from the C design. {Lecture}
  • Block-Level I/O Protocols
    Explains the different types of block-level protocols abstracted by
    the Vivado HLS tool. {Lecture, Lab}
  • Port-Level I/O Protocols
    Describes the port-level interface protocols abstracted by the
    Vivado HLS tool from the C design. {Lecture, Demo, Lab}
  • Port-Level I/O Protocols: AXI4 Interfaces
    Explains the different AXI interfaces (such as AXI4-Master,
    AXI4-Lite (Slave), and AXI4-Stream) supported by the Vivado
    HLS tool. {Lecture, Demo}
  • Port-Level I/O Protocols: Memory Interfaces
    Describes the memory interface port-level protocols (such as
    block RAM, FIFO) abstracted by the Vivado HLS tool from the C
    design. {Lecture, Lab}
  • Port-Level I/O Protocols: Bus Protocol
    Explains the bus protocol supported by the Vivado HLS tool.
  • Pipeline for Performance: PIPELINE
    Describes the PIPELINE directive for improving the throughput of
    a design. {Lecture, Demo, Lab}


Sessions 3 & 4
  • Pipeline for Performance: DATAFLOW
    Describes the DATAFLOW directive for improving the throughput
    of a design by pipelining the functions to execute as soon as
    possible. {Lecture, Lab}
  • Optimizing Structures for Performance
    Learn the performance limitations caused by arrays in your
    design. You will also learn some optimization techniques to
    handle arrays for improving performance. {Lecture, Demo, Lab}
  • Data Pack and Data Dependencies
    Learn how to use DATA_PACK and DEPENDENCE directives to
    overcome the limitations caused by structures and loops in the
    design. {Lecture}
  • Vivado HLS Tool Default Behavior: Latency
    Describes the default behavior of the Vivado HLS tool on latency
    and throughput. {Lecture}
  • Reducing Latency
    Describes how to optimize the C design to improve latency.
  • Improving Area and Resource Utilization
    Describes different methods for improving resource utilization and
    explains how some of the directives have impact on the area
    utilization. {Lecture, Lab}
  • HLx Design Flow – System Integration
    Describes the traditional RTL flow versus the Vivado HLx design
    flow. {Lecture, Lab}
  • Vivado HLS Tool C Libraries: Arbitrary Precision
    Describes the Vivado HLS tool support for the C/C++ languages,
    as well as arbitrary precision data types. {Lecture, Lab}
  • Hardware Modeling
    Explains hardware modeling with streaming data types and shift
    register implementation using the ap_shift_reg class. {Lecture}
  • Using Pointers in the Vivado HLS Tool
    Explains the use of pointers in the design and workarounds for
    some of the limitations. {Lecture}

Course Dates

29 Mar 2021 ONLINE EurAsia Enquire
6 Apr 2021 ONLINE Americas Enquire
15 Jun 2021 ONLINE EurAsia Enquire
20 Jul 2021 ONLINE EurAsia Enquire

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