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Python Lunch'n'Learn at DAC

This year at DAC54, Thursday is Training Day is making a guest appearance on Wednesday with the following Lunch'N'Learn:

Python for Scientific Computing and Machine Learning
Date & Time: Wednesday June 21st, 10:15 AM - 1:15 PM 
Location: Ballroom B - Austin Convention Center, TX
Presenter: John Aynsley, Doulos CTO
Cost: FREE

All attendees will recieve a free lunch kindly sponored by Synopsys, and a $25 "Thursday is Training Day" discount coupon!

Find out more and register »

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ARM & Doulos Tutorial at DAC 2017

Doulos is pleased to be presenting a tutorial with ARM at DAC 2017 in Austin, TX. 

Multicore Software Development on ARM 
Date & Time: Monday June 19, 10:30am - 12:00pm 
Location: 19AB - Austin Convention Center, TX
Presenter: Chris Shore, ARM & David C Black, Doulos

Find out more and register for DAC54»

Come and meet the Doulos team at booth #439 to find out about this event and the wide range of training courses

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Doulos Sponsors CDNLive EMEA 2017

Come and meet the Doulos team at CDNLive EMEA 2017! This conference will be held at the INFINITY Hotel & Conference Resort – Munich, Germany on May 15-17th, 2017.

Check out the full agenda and register for CDNLive EMEA »

CDNLive Silicon Valley 2017

Doulos Sponsors CDNLive Silicon Valley 2017

Come and meet the Doulos team at CDNLive Silicon Valley. This two day conference will be held at the Santa Clara Convention Center, CA on April 11-12th, 2017.

Check out the full agenda and register for CDNLive Silicon Valley »

CDNLive Silicon Valley 2017
Doulos at Verification Futures 2017

Doulos is pleased to be sponsoring Verification Futures 2017. This one day conference will be held in Reading, UK on April 6th, 2017.

Come and meet the team at the Doulos booth to find out about our range of verification training solutions.

VF 2017

Find out more and register for Verification Futures 2017 »

Doulos at Embedded World 2017

Embedded World 2017 Logo

Doulos is pleased to be exhibiting at Embedded World 2017. This three day conference will be held in Nürnberg, Germany on March 14-16th, 2017.

Come and meet the Doulos team in Hall 3 booth no. 555 to find out about our range of embedded systems training solutions. 

Find out more and register for Embedded World 2017 »

Doulos at DVCon United States 2017

Come and meet the Doulos team at booth 501 at DVCon United States 2017 on February 27th - March 2nd in San Jose, CA.

Doulos CTO, John Aynsley will be presenting "Doing Funny Stuff with the UVM Register Layer" on Tuesday, February 28th at 3pm - 4:30pm. 

DVCon US 2017

Find out more and register for DVCon United States 2017  »

Doulos at FPGA-forum 2017

Doulos is pleased to be exhibiting at FPGA-forum 2017. This two day conference will be held at the Royal Garden Hotel, Trondheim on February 15-16th, 2017.

Come and meet the team at the Doulos booth to find out about our range of training solutions.

FPGA Training

Find out more and register for FPGA-forum 2017 »

Doulos at ARM TechCon 2016

Doulos is delighted to be attending ARM TechCon 2016 on October 25-27th at the Santa Clara Convention Center, and will be co-presenting a training session with ARM® on the newly announced ARM Cortex®-M23 & Cortex-M33 processors:

ARM TechCon 2016

Developing software on the latest ARMv8-M processors for security solutions for IoT
Date: Wednesday, October 26th
Session Time: 10:30am - 11:20am
Presenters: David Black - Senior Member Technical Staff, Doulos
Joseph Yiu  - Senior Embedded Technology Manager, ARM
Find out more and register for this training »

Come and meet the team at the Doulos booth no. 1106 to find out about the very latest training on developing secure software for embedded applications.

ARM TechCon 2016 website »

Xilinx Training Webinar

Webinar: Timing Exception Constraints with Vivado
Date: October 21st, 2016
Duration: x1 1 hour session (international zones covered)
Presenter: Mike Smith, Specialist Xilinx Trainer
Summary: In this webinar you will learn when and how to use timing exceptions - constraints that modify the default timing analysis triggered by creating basic clock constraints - and simple input and output constraints. 

Find out more button

Doulos Webinars

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