Friday 3 April 2020

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Integrating the Arm Cortex-M3 in a Xilinx FPGA

FREE 1 hour webinar! Wednesday April 8, 2020 Register now below


A best-of-both worlds solution for embedded systems

The combination of the widely acclaimed Arm® Cortex®-M MCU architecture with the performance of a Xilinx® FPGA provides more flexibility and greater scope for innovation in the creation of application-optimised designs.

Many Vivado® users are familiar with the Microblaze™ RISC processor. However, the Arm Cortex-M3 has a substantially different hardware architecture, with unique system integration aspects.

In this webinar we will examine the Cortex-M3 IP block and discuss its integration inside a Xilinx FPGA.

We will:

  • Examine the two main system busses, their use model and restrictions
  • Review the operations of the Nested Vectored Interrupt Controller (NVIC) and its interaction with a Wakeup Interrupt Controller (WIC)
  • Examine the memory management operations along with invasive and non-invasive debugging features of the core.

Dr David Cabanis

Doulos Senior Member Technical Staff and Arm certified expert Dr David Cabanis will present this training webinar, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout.

Schedule and Registration:

This webinar will be broadcast twice, at convenient times for international audiences. Please review the times listed below and register for the most appropriate option for your time zone.

For Europe and Asia
  • Wednesday April 8, 2020
    Time: 10-11am (BST) 11am-12pm (CEST) 2.30-3.30pm (IST)
    Register Now

For Americas
  • Wednesday April 8, 2020
    Time: 10-11am (PDT) 11am-12pm (MDT) 12-1pm (CDT) 1-2pm (EDT)
    Register Now

If you have any queries, please contact

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