Common Mistakes in SystemVerilog
FREE 1 hour webinar! Friday February 28, 2020 Register now below
This webinar will explore the most common mistakes users of SystemVerilog make. These mistakes have been identified by observing the lab work of students participating in Doulos training classes. The webinar aims to help you avoid the pitfalls and, in the process, get your designs working faster.
Doulos CTI Doug Perry, will explore the topics listed below and provide useful tips and resources to help you. Practical examples will be provided using the online simulation environment EDA Playground. The webinar will include live interactive Q&A participation for attendees with Doulos technical experts.
Topics include:Changing Wire Assignments
Static vs Automatic Variables
Static vs Automatic Tasks
Equality between Vectors
Schedule and Registration:This webinar will be broadcast twice, at convenient times for international audiences. Please review the times listed below and register for the most appropriate option for your time zone.
For Europe and Asia
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SystemVerilog training and resources available NOW from Doulos:
- Range of classes available – Find our more about SystemVerilog – face-to-face training »
- SystemVerilog Golden Reference Guide - the perfect project companion - Buy online »
- Free online support resources including video tutorials – visit www.doulos.com/knowhow »
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Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.