Thursday 28 May 2020

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Common Mistakes in SystemVerilog

FREE 1 hour webinar! Friday February 28, 2020 Register now below

Webinar Overview:

This webinar will explore the most common mistakes users of SystemVerilog make. These mistakes have been identified by observing the lab work of students participating in Doulos training classes. The webinar aims to help you avoid the pitfalls and, in the process, get your designs working faster.

Doug Perry Doulos CTI Doug Perry, will explore the topics listed below and provide useful tips and resources to help you. Practical examples will be provided using the online simulation environment EDA Playground. The webinar will include live interactive Q&A participation for attendees with Doulos technical experts.

Topics include:

Changing Wire Assignments
Static vs Automatic Variables
Static vs Automatic Tasks
Assignment Timing
Enumerations
struct
Equality Operators
Equality between Vectors
Temporal Behaviour

Schedule and Registration:

This webinar will be broadcast twice, at convenient times for international audiences. Please review the times listed below and register for the most appropriate option for your time zone.

For Europe and Asia
  • Friday February 28, 2020
    Time: 10-11am (GMT) 11am-12pm (CET) 3.30-4.30pm (IST)
    Register Now

For Americas
  • Friday February 28, 2020
    Time: 10am-11am (PST) 11am-12pm (MST) 12-1pm (CST) 1-2pm (EST)
    Register Now


If you have any queries, please contact info@doulos.com




SystemVerilog training and resources available NOW from Doulos:





SystemVerilog training from Doulos:
Comprehensive SystemVerilog
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Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.

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