Tuesday 22 May 2018

Developing & Delivering KnowHow

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Common Mistakes in SystemVerilog

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Webinar Overview:

This webinar will explore the most common mistakes users of SystemVerilog make. These mistakes have been identified by observing the lab work of students participating in Doulos training classes. The webinar aims to help you avoid the pitfalls and, in the process, get your designs working faster.

Doug Perry Doulos Senior Member Technical Staff Doug Perry, will explore the topics listed below and provide useful tips and resources to help you. Practical examples will be provided using Aldec Riviera-PRO™ in the online simulation environment EDA Playground. The webinar will include live interactive Q&A participation for attendees with Doulos technical experts.

Topics include:

Changing Wire Assignments
Static vs Automatic Variables
Static vs Automatic Tasks
Assignment Timing
Enumerations
struct
Equality Operators
Equality between Vectors
Temporal Behaviour

If you have any queries, please contact info@doulos.com




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