Friday 14 August 2020

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Common Mistakes in VHDL

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Webinar Overview:

VHDLLearning any new programming language will undoubtedly be influenced by your existing design experience, and although that knowledge is largely very useful it can also work against you... For example, when you come to learn VHDL, the parallel nature of the hardware design language might trip you up if you've been using a language that has a sequential nature, such as Java, C or C++.

Doug Perry In this webinar Doulos Certified Training Instructor and VHDL guru, Doug Perry, (author of "VHDL: Programming by Example") explores some of the common mistakes designers make when starting out with VHDL and provides useful tips and resources for getting on track. Practical examples will be provided using Aldec Riviera-PRO™ in the online simulation environment EDA Playground.

The webinar includes live interactive Q&A participation for attendees with Doulos technical experts.

Content Summary:

VHDL Statements
Process Statements
Signal Assignments
Delta Delays
The Simulation Cycle
Incomplete Assignments
Unexpected Latches

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Scheduled related training from Doulos in 2015:
Comprehensive VHDL
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Expert VHDL
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