Synthesis of SystemVerilog RTL Constructs
FREE 1 hour webinar On-Demand Register now below
SystemVerilog offers many new register-transfer level constructs, allowing for more concise RTL coding as well as the specification of design intent for simulation, synthesis and formal verification.
This webinar will help you understand the new synthesizable RTL constructs including the three new types of always blocks, priority, unique, wild equality, case inside, inside operator and streaming operators.
You can expect to learn about:
- how to use the RTL constructs for more concise RTL coding,
- specifying design intent,
- examining the simulation and synthesis results.
Practical examples will be provided using Synopsys VCS® in the free online simulation environment EDA Playground.
Doulos Senior Member Technical Staff Brian Jensen will present this training webinar, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout.
If you have any queries, please contact firstname.lastname@example.org
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