Getting into SystemVerilog from VHDL:
Guidance from a VHDL Guru
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In this webinar Doulos Senior Member Technical Staff, Doug Perry (author of 'Programming By Example') will provide a VHDL Guru's perspective on SystemVerilog and UVM. Doug will look at the language features of SystemVerilog, contrasting them with what is available in VHDL, and highlighting the challenges of making the transition.
Coding examples will be shown running on Aldec Riviera-PRO™.
This training webinar will consist of a one-hour broadcast with interactive Q&A available to attendees throughout.
Attendance is free of charge.
Content Summary:What is SystemVerilog? Language evolution Language features Standard verification methodologies References Q&A
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