Wednesday 15 August 2018

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Getting into SystemVerilog from VHDL:
Guidance from a VHDL Guru - ON-DEMAND

Format: On-Demand Training Webinar
Duration: 1 hour
Cost: FREE!
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Webinar Overview:

In this webinar Doulos Senior Member Technical Staff, Doug Perry (author of 'Programming By Example') provides a VHDL Guru's perspective on SystemVerilog and UVM. Doug looks at the language features of SystemVerilog, contrasting them with what is available in VHDL, and highlighting the challenges of making the transition.

John AynsleyA coding example is shown running on Aldec Riviera-PRO™ in EDA Playground.

Running Time: 62 minutes

Content Summary:

What is SystemVerilog? Language evolution Language features Standard verification methodologies References Q&A

This webinar has been recorded.

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SystemVerilog training and resources available NOW from Doulos:





Scheduled Verification Training from Doulos in 2015:
Comprehensive VHDL
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Expert VHDL
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Comprehensive SystemVerilog
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SystemVerilog for Designers
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SystemVerilog for
Verification Specialists

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UVM Adopter Class
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View full training schedule »  
Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.

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