Getting into SystemVerilog from VHDL:
Format: On-Demand Training Webinar
Guidance from a VHDL Guru - ON-DEMAND
Duration: 1 hour
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In this webinar Doulos Senior Member Technical Staff, Doug Perry (author of 'Programming By Example') provides a VHDL Guru's perspective on SystemVerilog and UVM. Doug looks at the language features of SystemVerilog, contrasting them with what is available in VHDL, and highlighting the challenges of making the transition.
A coding example is shown running on Aldec Riviera-PRO™ in EDA Playground.
Running Time: 62 minutes
Content Summary:What is SystemVerilog? Language evolution Language features Standard verification methodologies References Q&A
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