Monday 13 July 2020

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SystemVerilog Online Training

Synthesis-Friendly SystemVerilog

Format: Training Webinar
Duration: 1 hour
Cost: FREE!
Schedule and Registration: Recording Available (see below - registration required)

Webinar Overview:

Although SystemVerilog is perhaps most widely used in the context of hardware verification, it also contains many features directly relevant to the hardware designer. We explore the features of SystemVerilog that are useful for RTL synthesis, showing how the RTL SystemVerilog language constructs have been optimized for productivity and reliability.

We start from the basic principles of RTL coding style in SystemVerilog, then focus on the language features that allow hardware designers to work very efficiently while at the same time avoiding synthesis pitfalls.

John Aynsley Doulos CTO John Aynsley presents this training webinar, which consists of a one-hour session.

And... it's FREE!

Content Summary:

Introduction Modules, ports, parameters, and hierarchy Assignments and procedures Control constructs and operators Hardware-oriented data types Combinational and clocked logic Q&A

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What is SystemVerilog Out of the Box?
SystemVerilog Out of the Box is a unique blend of training and KnowHow resources designed to help you maximise the potential of SystemVerilog where you need it.

SystemVerilog training and resources available NOW from Doulos:

Verification Training from Doulos:
Expert VHDL Verification
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Comprehensive SystemVerilog
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SystemVerilog for Designers
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SystemVerilog for
Verification Specialists

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OVM Adopter Class
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UVM Adopter Class
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View full training schedule »  
Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.

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