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SystemVerilog Online Training

Synthesis-Friendly SystemVerilog

Format: Live on-line training event
Duration: 1 hour
Cost: FREE!
Schedule and Registration: Register below

Webinar Overview:

Although SystemVerilog is perhaps most widely used in the context of hardware verification, it also contains many features directly relevant to the hardware designer. We explore the features of SystemVerilog that are useful for RTL synthesis, showing how the RTL SystemVerilog language constructs have been optimized for productivity and reliability.


We start from the basic principles of RTL coding style in SystemVerilog, then focus on the language features that allow hardware designers to work very efficiently while at the same time avoiding synthesis pitfalls.

John Aynsley Doulos CTO John Aynsley will be broadcasting this training webinar, on November 2nd, which will consist of a one-hour session, (see below for details) and will be interactive with Q&A participation from delegates.

And... it's FREE!

Content Summary:

Introduction Modules, ports, parameters, and hierarchy Assignments and procedures Control constructs and operators Hardware-oriented data types Combinational and clocked logic Q&A

Schedule and Registration:

This webinar will be broadcast twice, at convenient times for international audiences. Please review the times listed below and register for the most appropriate option to your time zone.

For UK, Europe and Asia
  • Friday November 2nd, 2012
    Time: 9am-10am (GMT - UK) 10am-11am (CET) 2.30pm-3.30pm (IST)

Register Now

For North America (also UK and Europe if late afternoon preferred)
  • Friday November 2nd, 2012
    Time: 10am-11am (PDT) 1pm-2pm (EDT) 5pm-6pm (GMT - UK)

Register Now


If you have any queries, please contact info@doulos.com



What is SystemVerilog Out of the Box?
SystemVerilog Out of the Box is a unique blend of training and KnowHow resources designed to help you maximise the potential of SystemVerilog where you need it.



SystemVerilog training and resources available NOW from Doulos:





Scheduled Verification Training from Doulos in 2012:
Expert VHDL Verification
Dates / info / register »
Comprehensive SystemVerilog
Dates / info / register »
SystemVerilog for Designers
Dates / info / register »
SystemVerilog for
Verification Specialists

Dates / info / register »
OVM Adopter Class
Dates / info / register »
UVM Adopter Class
Dates / info / register »
View full training schedule »  
Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.

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