Wednesday 19 December 2018

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Quick Start to Timing Constraints with Vivado

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Getting up and running with timing constraints and analysis


This webinar provides you with an insight into timing constraints and static timing analysis: techniques that are instrumental to successful FPGA development. Building your understanding will help you meet timing closure, successfully interface to high performance I/O, and reduce your development time.

Xilinx® Design Constraints (XDC) are based on the industry-standard Synopsys® Design Constraints (SDC). There are key differences between XDC, which the Vivado® Design Suite uses, and the legacy User Constraints Format (UCF) that was used with earlier tools. We see where XDC timing constraints are used in the Vivado Design Suite and introduce the basic constraints for creating clocks and specifying I/O timing. We also get to grips with the terminology that the static timing analysis engine uses and the format of the timing reports it generates.

Mike SmithSpecialist Xilinx Trainer, Mike Smith, from Doulos will be broadcasting this training webinar, which will consist of a one-hour session, (see below for details) and will be interactive with Q&A participation from delegates.

And... this webinar is FREE to attend!

Content Summary:

How timing constraints are used in the Vivado Design Suite
Timing paths; launch and capture edges; source and destination clocks;
setup and hold requirements
Anatomy of a timing report; setup and hold checks; slack calculation
Generated clocks; auto-derived clocks
Setting input and output delays; minimum and maximum delays
Timing reports for inputs and outputs
Timing Closure Methodology: Baselining




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