Friday 14 August 2020

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Webinar Training Event

How to Take Advantage of UVM 1.2 Right Now

Duration: 1 hour
Cost: FREE!
Schedule: On Demand - See below (registration required)

In this webinar:

Find out how to take advantage of new features and improvements in UVM 1.2
Get expert advice on migration to UVM 1.2 from earlier versions
Try working code examples yourself using Synopsys VCS on EDA Playground

With UVM up for IEEE standardization, now is a great time to find out about what's new in UVM 1.2 and how to plot your migration path. So make sure you attend this webinar presented by Doulos CTO John Aynsley (recognised* for his industry contribution to standardization).

You will also find out how to avoid significant migration traps associated with:
deprecated features
backward compatibility and
compromising simulation speed.

Working examples of UVM 1.2 code will be illustrated using the Synopsys VCS® functional verification solution.

During the webinar, you will be provided with links to worked examples and you are welcome to try them out yourself online with VCS on EDA Playground (

This training webinar will consist of a one-hour session, (see below for details) and will be interactive with Q&A participation from delegates.

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If you have any queries, please contact

John AynsleyJohn Aynsley
is co-founder and CTO of industry training specialists Doulos, where he drives technical strategy and execution. John has spent his entire career working in EDA, specializing in hardware description and verification languages, in particular SystemVerilog, SystemC and VHDL.

He was co-author of the IEEE Standard 1666-2005 SystemC Language Reference Manual and author of the OSCI TLM-2.0 Language Reference Manual. More recently he served as technical lead and author of the IEEE Standard 1666-2011 SystemC Language Reference Manual, as well as implementing the 1666-compliance regression test suite for the Accellera Systems Initiative proof-of-concept SystemC simulator.

* In February 2012 John was recognised for his contribution to SystemC standardization when he received the Accellera Systems Initiative Technical Excellence Award.

UVM training and resources available NOW from Doulos:

Scheduled Verification Training from Doulos in 2012:
UVM Adopter Class
Dates / info / register »
Comprehensive SystemVerilog
Dates / info / register »
SystemVerilog for
Verification Specialists

Dates / info / register »
View full training schedule »  
Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.

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