Friday 14 August 2020

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Getting Zynq up and running with your HDL design IP

Format: Training webinar
Duration: 1 hour
Cost: FREE!
Please email Doulos to be notified when this webinar will next run.

Webinar Overview:

So you have your Zynq®-7000 All Programmable SoC based board! Your carefully crafted VHDL or Verilog design is ready to go, but what about integrating the HDL IP within the ARM® Cortex®-A9 sub-system?

AXI protocols, IP integration, Bare-metal testing, what do they all mean? This one-hour webinar is here to answer all of these fundamental questions that HDL designers face when they start their Zynq journey.

Using the EnSilica Zynq based board, we illustrate how to drive Vivado to generate a hierarchical design comprising the Cortex-A9 MPCore and an HDL design using multiple AXI interfaces. We will examine the implementation of the AXI protocol logic and finally, to provide a complete picture, we will write bare-metal code to validate our newly integrated HDL IP on the Cortex-A9.

This webinar has been developed in collaboration with EnSilica and will rely on the use of the eSi-ZM1 module.

David Cabanis Doulos Senior Member Technical Staff, and ARM expert Dr David Cabanis will be the instructor on this training webinar, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout.

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