Thursday 24 May 2018

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On-line Training

VHDL versus SystemVerilog versus SystemC

Format: Live webinar
Duration: 1 hour
Cost: FREE!
Please email Doulos to be notified when this webinar will next run.

Webinar Overview:

What languages are you using now, and what languages will you be using in 2 years time? Grab another chance to view this webinar in which we compare and contrast the adoption and use of VHDL, SystemVerilog, and SystemC for hardware design, RTL synthesis, high-level synthesis, hardware verification, system modeling, and virtual prototyping. We give you an insight into how each of these languages are being used and their relative strengths and weaknesses. We also explain how the three languages can be used together in the same mixed-language environment.

John AynsleyDoulos CTO, John Aynsley, will be broadcasting this training webinar, which will consist of a one-hour session, (see below for details) and will be interactive with Q&A participation from delegates.

Attendance is FREE!


If you have any queries, please contact info@doulos.com


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Training available NOW from Doulos:

Scheduled Verification Training from Doulos in 2012:
Comprehensive VHDL More information / enquire »
Comprehensive SystemVerilog
More information / enquire »
Comprehensive SystemC
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Full range of Doulos training »  
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