Acceleration-Ready UVM

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Webinar Overview:

The use of emulators and FPGA-based accelerators to speed up execution times for functional verification is increasing. At the same time, SystemVerilog and UVM have become the dominant language and methodology for writing functional verification environments for simulation.

In this webinar, we explain how to write or modify a UVM verification environment to gain maximum benefit when using a hardware accelerator or emulator. Using the Easier™ UVM Coding Guidelines, we explain how to partition the UVM verification environment between the host computer and the accelerator to optimize execution speed. We explain how the SCE-MI standard is used for communication between host and accelerator. Finally, we step through the compilation and execution flow for running a UVM simulation with an accelerator box.

Doulos CTO John Aynsley and Hardware Verification Products Manager of Aldec Krzysztof Szczur, will present this training webinar, which will consist of a one-hour broadcast with interactive Q&A available to attendees throughout.

Attendance is free of charge.

UVM training and resources available NOW from Doulos:

• UVM Adopter Class: full SystemVerilog verification project readiness in 3 days »
• UVM Golden Reference Guide: the perfect companion in any UVM project - Buy online »
• Free online support resources including video tutorials – visit www.doulos.com/easier »