Advanced VHDL Verification - OS-VVM and more...
Format: Training webinar
Duration: 1 hour
Schedule and Registration: Recording Available (see below - registration required)
Are you using VHDL for verification of complex designs, and wondering if you should move to UVM and SystemVerilog? This webinar will introduce you to Open Source VHDL Verification Methodology (OS-VVM): what it does, how to use it, and how it compares with UVM.Consultant Engineer, Alan Fitch, presents this training webinar, which consists of a one-hour session.
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