Doulos at DAC 2017
June 18-22: Austin, TX
Make sure you include Doulos in your DAC experience this year:
- June 19: Monday Tutorial: Multicore Software Development on ARM
- June 21: Free Lunch'n'Learn: Python for Scientific Computing & Machine Learning
- June 21: Presentation: Formal Verification - Come on Man, Go For It!
- June 22: Thursday is Training Day: Official DAC training
MONDAY TUTORIAL: Multicore Software Development on ARM
Monday June 19: 10:30am - 12:00pm Room 19AB
Chris Shore of ARM (view his blog on ARM Community) will examine multicore software architectures and provide a comprehensive tutorial on the architectural and implementation features of hardware platforms which make them possible, and David C Black of Doulos will then look at the higher-level aspects of designing and architecting a software system to exploit a multiprocessing architecture.
LUNCH'N'LEARN: Python for Scientific Computing & Machine Learning
Wednesday June 21: 12.15 - 1.15pm Ballroom D
Attend our taster session FREE OF CHARGE - and you will discover some really cool things you can do with Python to help you start making sense of the emerging libraries and frameworks being used for Deep Learning and Scientific Computing.This session includes:
- One hour presentation by Doulos CTO, John Aynsley
- Free box lunch, kindly sponsored by Synopsys
- Discount voucher valid towards Thursday is Training Day
Wednesday June 21: 2.00pm
Join Doulos CTO, John Aynsley on the Verification Academy Booth (#429) at DAC for a reality check on Formal Verification.
The tool vendors tell us that formal verification is now ready for general use, and you don't need a PhD to use it. Meanwhile, big companies continue to recruit formal PhDs into their verification teams while other less-well-qualified engineers seem reluctant to go beyond simplified formal "apps". So, what is the truth of the matter? Can non-specialist engineers become productive with formal?
Thursday June 22: 10.15am - 5.15pm
Thursday is Training Day provides an opportunity for you to attend high-quality training in popular subjects as part of your DAC experience. Two of the three tracks this year are provided by Doulos, taught by well respected instructors who are each subject matter experts in their own right and have wide experience of teaching engineers at all skill levels.
Use the links below to find out more and register for this great value training.
|How to Build Class-Based Verification Environments in SystemVerilog
10:15 AM - 1:15 PM - Ballroom E
|Learn UVM using the Easier UVM Coding Guidelines and Code Generator
2:15 PM - 5:15 PM - Ballroom E
|Formal Verification Using SystemVerilog Assertions
10:15 AM - 1:15 PM - Ballroom F
| The Python Language: Become a Pythoneer!
2:15 PM - 5:15 PM - Ballroom F
Attend both the morning and afternoon sessions from the same track, or mix-and-match sessions from two different tracks, or attend just a single half-day session.
VIDEO INTERVIEWS WITH PREVIOUS DAC ATTENDEES
Doulos has set the industry standard for developing and delivering high quality training and know-how in electronic system design and verification for over 25 years, covering languages and methodologies for system, hardware, and embedded software designers. The essential choice for more than 3000 companies across over 60 countries, Doulos provides scheduled classes across North America, Europe and India, and delivers on-site, team-based training and interactive on-line learning events worldwide.
Doulos is dedicated to providing engineers with useful technical information, models, guidelines, tips and downloads.
Check out these free KnowHow resources here »