UVM Online Training
Easier UVM Register LayerFormat: Live on-line training event
Duration: 1 hour
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What is Easier UVM Register Layer?
Just as UVM simplifies developing tests and testbenches, UVM also provides a simple way to model and access registers inside a design. This is known as the register layer. The UVM register layer has a simple user interface, but the plethora of features can be daunting and non-intuitive for beginners.
Easier UVM Register Layer is the perfect starting point for design and verification engineers seeking to simplify their test development, register testing, and design checking, and to maximize their verification reuse.
In this webinar Doulos Senior Consultant Dr David Long helps you to make sense of the UVM register layer. He covers the purpose of the register layer, explains the user interface, as well as how to construct a register model, integrate it into a verification environment, use it in tests and take advantage of the built-in register tests.
The training consists of a one-hour session, (see below for details) and the live event is interactive with Q&A participation from delegates.
And yes – it's FREE!
Content Summary:Purpose and use of a register model register layer user interface How to create a register model How to integrate a register model How to use a register model in tests UVM's built-in register tests
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What is Easier UVM?
Easier UVM is a set of guidelines for learning and using UVM, the Universal Verification Methodology for SystemVerilog and is aimed at mainstream designers rather than power users specialising in verification.
UVM training and resources available NOW from Doulos:
- UVM Adopter Class – full SystemVerilog verification project readiness in 3 days – face-to-face training »
- UVM Golden Reference Guide - the perfect companion in any UVM project - Buy on-line »
- Free on-line support resources including video tutorials – visit www.doulos.com/knowhow »
Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.