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UVM Online Training

Easier UVM Register Layer

Format: Live on-line training event
Duration: 1 hour
Cost: FREE!
Schedule and Registration: Register below

Webinar Overview:

What is Easier UVM Register Layer?
Just as UVM simplifies developing tests and testbenches, UVM also provides a simple way to model and access registers inside a design. This is known as the register layer. The UVM register layer has a simple user interface, but the range of features can be daunting and non-intuitive for beginners.

Easier UVM Register Layer is the perfect starting point for design and verification engineers seeking to simplify their test development, register testing, and design checking, and to maximize their verification reuse.

Dr David Long Doulos Principal Member of Technical Staff Dr David Long will be broadcasting this live training webinar, on December 13th, that will help you to make sense of the UVM register layer.

He will cover the purpose of the register layer and explain the user interface, as well as how to construct a register model, integrate it into a verification environment, use it in tests and take advantage of the built-in register tests.

The training will consist of a one-hour session, (see below for details) and will be interactive with Q&A participation from delegates.

Attendance is FREE!

Content Summary:

Purpose and use of a register model register layer user interface How to create a register model How to integrate a register model How to use a register model in tests UVM's built-in register tests

Schedule and Registration:

This webinar will be broadcast twice, at convenient times for international audiences. Please review the times listed below and register for the most appropriate option to your time zone.

For UK, Europe and Asia
  • Friday December 13th, 2013
    Time: 9am-10am (GMT - UK) 10am-11am (CET) 2.30pm-3.30pm (IST)

Register Now

For North America (also UK and Europe if late afternoon preferred)
  • Friday December 13th, 2013
    Time: 9am-10am (PST) 12pm-1pm (EST) 5pm-6pm (GMT - UK)

Register Now


If you have any queries, please contact info@doulos.com



What is Easier UVM?
Easier UVM is a set of guidelines for learning and using UVM, the Universal Verification Methodology for SystemVerilog and is aimed at mainstream designers rather than power users specialising in verification.



UVM training and resources available NOW from Doulos:





Scheduled Verification Training from Doulos in 2013:
Comprehensive VHDL
More info / register »
Nov 18th
Nov 25th
Dec 2nd
Dec 9th
Dec 16th
Paris, FR
Kista, SE
San Jose, CA
Ringwood, UK
Munich, DE
Expert VHDL
More info / register »
Nov 18th
Nov 25th
Dec 2nd
Dec 9th
Munich, DE
Paris, FR
Columbia, MD
Ringwood, UK
Comprehensive SystemVerilog
More info / register »
Nov 25th
Nov 25th
Ringwood, UK
Munich, DE
UVM Adopter Class
More info / register »
Nov 18th
Dec 9th
Dec 9th
Dec 16th
San Jose, CA
Ringwood, UK
Munich, DE
Columbia, MD
View full training schedule »    
Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.

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