Sunday 21 October 2018

Developing & Delivering KnowHow

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UVM Online Training

Easier UVM - Functional Verification
for Mainstream Designers

Format: Live webinar
Duration: 2 hours (two 1 hour sessions)
Cost: FREE!
Date: Recording Available (see below)

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Webinar Overview:

  • Still writing test benches in Verilog or VHDL? Need a better approach to improve your functional verification?
  • Need help with the transition from Verilog or VHDL to SystemVerilog?
  • Looking for guidance on learning and using UVM, the Universal Verification Methodology for SystemVerilog?

Dr David Long
Doulos Senior Consultant Dr David Long presents a two-part training webinar, to help you tackle these questions.

The training consists of 2 one-hour sessions.

Register Now

Content Summary:

Session 1: Introducing Easier UVM • Components • Transactions • Sequences • Phases • Ports • TLM • Factory overrides • Q&A

Session 2: Generation • Configuration • Starting a test • Ending a test • Layered sequences • Requests and responses • Copying and comparing transactions • Q&A

And yes – it's FREE!

If you have any queries, please contact info@doulos.com



What is Easier UVM?
Easier UVM is a set of guidelines for learning and using UVM, the Universal Verification Methodology for SystemVerilog and is aimed at mainstream designers rather than power users specialising in verification.



UVM training and resources available NOW from Doulos:





Scheduled Verification Training from Doulos in 2012:
Expert VHDL Verification
Dates / info / register »
Comprehensive SystemVerilog
Dates / info / register »
SystemVerilog for Designers
Dates / info / register »
SystemVerilog for
Verification Specialists

Dates / info / register »
OVM Adopter Class
Dates / info / register »
UVM Adopter Class
Dates / info / register »
View full training schedule »  
Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.

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