Thursday 24 May 2018

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Understanding Random Stability in SystemVerilog and UVM

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Webinar Overview:


A common issue with constrained random simulation is being able to reproduce random stimulus for debug purposes and for locking down regressions test suites. This is especially problematic when the source code needs to be modified, and is known in SystemVerilog as random stability.


In this webinar, we explain:

  • random stability in SystemVerilog and in UVM, the Universal Verification Methodology
  • the pitfalls of poor random number generation and seeding
  • how to ensure that simulation results are reproducible in native SystemVerilog and in UVM through a careful presentation of hierarchical seeding, manual seeding, thread stability, and object stability
  • exactly what changes you can and cannot make to UVM code without disturbing the random stimulus generation.


John Aynsley Examples written in the IEEE Std 1800™ SystemVerilog language and UVM 1.2 will be shown running on the Cadence® Incisive® Enterprise Simulator.

This training webinar is presented by Doulos CTO, John Aynsley and will consist of a one-hour broadcast with interactive Q&A available to attendees throughout. Attendance is free of charge.



SystemVerilog training and resources available NOW from Doulos:





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