Friday 7 August 2020

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Home > Events > How to take advantage of UVM-style run-time configuration in VHDL

How to take advantage of UVM-style
run-time configuration in VHDL

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Webinar Overview:

UVM users are familiar with using the UVM configuration database to control test settings. This allows you to run multiple different tests without having to recompile the testbench. But what if you're currently a VHDL user? Do you have to change to UVM just to get run-time configuration?

In this webinar we will

  • discuss the requirements for run-time configuration
  • give a brief overview of configuration methods in UVM (factory, config_db, command line)
  • look at the options for VHDL including tool specific Tcl and VHDL top level generics
  • show how a VHDL package can be written to emulate some of the features of the UVM configuration database
  • summarise the pros and cons of the different approaches

Alan Fitch

Find out how to run multiple different tests without the overhead of compiling.

Principal Member of Technical Staff, Alan Fitch, will be broadcasting this training webinar, which will consist of a one-hour session, (see below for details) and will be interactive with Q&A participation from attendees.
If you have any queries, please contact

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