Monday 21 January 2019

Developing & Delivering KnowHow

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Workshop detail and schedule

Workshop benefits:

Register NowThis workshop will help you get a head-start in grasping the
critical developments in ASIC and FPGA verification by giving you:

  • an understanding of the solutions and challenges in contemporary verification
  • a clear view of using object oriented approaches to verification
  • an introduction to the key features and capabilities of the leading industry languages through practical examples
  • knowledge of key areas where applying these techniques can improve your efficiency and quality
  • an informed view of which developments are important to your current projects and future potential.

Full schedule:

08.30 Registration

09.00 Pre-training questionnaire & live polling

09.15 Improving the Verification Process

    • Planning
    • Automatic generation of test vectors
    • Metrics to ensure comprehensive testing
    • Using properties
    • Testbench architecture
    • Transaction-level modelling
    • Class-based environments
    • Standards and Verification IP

10.30 Morning refreshments and networking

11.00 Enhancements to VHDL Testbenches

    • Useful VHDL 2008 features
    • Open-Source VHDL Verification Methodology (OS-VVM)
    • Constrained-Random Vectors
    • Functional Coverage

12.00 Creating Virtual Prototypes and Testbenches in SystemC

    • Introduction to SystemC language and features
    • Transaction Level Modelling Standard
    • Use of basic protocol and generic payload
    • Constrained-Random Transactions and Transaction Recording
    • The Control, Configuration and Introspection (CCI) Standard for Verification IP

13.00 Lunch and networking

14.00  SystemVerilog features for Verification

    • Classes for Transactions and Verification Components
    • Using Interfaces to separate class-based verification environment from RTL Device-Under-Test (DUT) and associated test harness
    • Specifying constraints
    • Setting up functional coverage
    • Writing properties and sequences

15.30  Afternoon break and networking

16.00 The Universal Verification Methodology (UVM)

    • Overview of UVM class library and features
    • Creating a UVM environment
    • Writing a sequence to drive the DUT
    • Setting up the environment for a specific test
    • Use of the Register Layer

17.30 Conclusions and Closing Remarks

    • Strengths and weaknesses of each methodology
    • Selecting the most appropriate methodology for your design
    • Mixed-language testbenches
    • Future Directions?

18.00 Post-training live polling and calculating ROI of attending this training

18.15 Close of the conference
Register Now

Dr David LongTrainer: Dr David Long: Principal Member, Technical Team

Dr Long has been a key member of the Doulos technical team since 2001, specialising in Hardware Description Language-based design and verification...

Find out more about this Doulos trainer »

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Contact information:

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