Transform Slow Software into Fast Hardware on a Zynq® All Programmable SoC using Vivado® HLS and SystemC/TLM-2.0
Format: Online training event
Duration: 1 hour
Registration: Let me know when this webinar will run again
Another chance to view this webinar in which you will learn how to take a complex mathematical function that was found to run too slowly in software and transform it into a high performance hardware submodule within Zynq®. Before making the transformation, we will show you how to model the hardware submodule in SystemC/TLM-2.0 to provide assurance that once the hardware is implemented, performance will meet expectations.
This webinar will demonstrate the tool flow from concept to FPGA implementation by using Xilinx Vivado® HLS and Vivado IP Integrator. The source code of the examples will be made available to all who attend.
Attendance is FREE!
If you have any queries, please contact firstname.lastname@example.org
What is SystemC?
Developed by a group of companies forming the Open SystemC Initiative (OSCI), SystemC is a C++ class library typically used to model systems that have hardware and software content at the transaction level of abstraction.
SystemC and Xilinx training and resources available NOW from Doulos:
- Comprehensive SystemC – a 5-day training class introducing SystemC »
- Xilinx Zynq System Architecture – learn to effectively architect a Zynq All Programmable system on a chip »
- Xilinx Vivado Adopter Class – get the most out of your transition to the Vivado Design Suite »
- SystemC Golden Reference Guide - the perfect companion in any SystemC project - Buy on-line »
- Free on-line support resources including video tutorials – visit www.doulos.com/knowhow »
Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.