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Transform Slow Software into Fast Hardware on a Zynq® All Programmable SoC using Vivado® HLS and SystemC/TLM-2.0


Format: Online training event
Duration: 1 hour
Cost: FREE!
Schedule and Registration:
Monday December 9th, 2013 - Register below


SystemC Zynq

Webinar Overview:

In this webinar you will learn how to take a complex mathematical function that was found to run too slowly in software and transform it into a high performance hardware submodule within Zynq®. Before making the transformation, we will show you how to model the hardware submodule in SystemC/TLM-2.0 to provide assurance that once the hardware is implemented, performance will meet expectations.

This webinar will demonstrate the tool flow from concept to FPGA implementation by using Xilinx Vivado® HLS and Vivado IP Integrator. The source code of the examples will be made available to all who attend.

David Black The rescheduled session will be presented by David C Black, Doulos Senior Member of Technical Staff and co-author of "SystemC: From the Ground Up", and will be broadcast on December 9th. It will consist of a one-hour session, (see below for details) and will be interactive with Q&A participation from delegates.

Attendance is FREE!


Schedule and Registration:

This webinar will be broadcast twice, at convenient times for international audiences. Please review the times listed below and register for the most appropriate option to your time zone.

For UK, Europe and Asia
  • Friday December 9, 2013
    Time: 12pm-1pm (GMT - UK) 1pm-2pm (CET) 5.30pm-6.30pm (IST)

Register Now


If you have any queries, please contact info@doulos.com



What is SystemC?
Developed by a group of companies forming the Open SystemC Initiative (OSCI), SystemC is a C++ class library typically used to model systems that have hardware and software content at the transaction level of abstraction.



SystemC and Xilinx training and resources available NOW from Doulos:





Scheduled Training from Doulos in 2013:
Comprehensive SystemC
Dates / info / register »
SystemC Modeling Using TLM-2.0
Dates / info / register »
Xilinx Zynq System Architecture
Dates / info / register »
Xilinx Vivado Adopter Class
Dates / info / register »
Xilinx Vivado HLS
Dates / info / register »
View full training schedule »  
Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.

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