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Doulos picks up awards at SNUGs

Doulos supported the Ottawa and Boston Synopsys User Group events (SNUGs) recently. Doug Smith and David Long delivered the paper entitled: Stick a fork in it: Applications for SystemVerilog Dynamic Processes.

They were awarded 2nd Best Paper at the Ottawa SNUG and 3rd Best Paper at the Boston SNUG.

Click here to downlod the full paper and the slides in PDF format.

Doulos joins System Realization Alliance

As a longstanding global training partner for ARM based system design Doulos is extending its partnership with Cadence by joining the newly announced System Realization Alliance.

This collaboration between ARM and Cadence is all about the development of more productive system level design and verification methodologies; and critically enabling their adoption by end users.

Rob Hurley, Doulos CEO, said, 'With our key and unique capabilities in know-how transfer in the field of transaction level modeling and verification, Doulos look forward to contributing strongly to this initiative.'

Click here to find out more

RapidGain Actel ARM Cortex M3 - new dates scheduled!

The RapidGain events below will be focused on Actel's SmartFusion Mixed Signal FPGAs and are being delivered in partnership with MSC

Course Dates:
September 21st, 2010 Zurich, CH
September 22nd, 2010 Stuttgart, DE
September 23rd, 2010 Munich, DE
September 27th, 2010 Hamburg, DE
September 28th, 2010 Berlin, DE
September 30th, 2010 Paris, FR


Click here for more details or to enquire.

Doulos releases 3 day UVM Adopter Class at DAC Anaheim

At Last, One Functional Verification Methodology for Everyone!

Adding to the broadest verification training program available already covering methodology standards VMM and OVM, Doulos announces support for the single Universal Verification Methodology recently released by Accellera.

Doulos has been pleased to work in close co-operation with its partners in the EDA industry to ensure early availability of this key training program.

Available for delivery worldwide from July, this 3 day class enables verification teams to gear up for the fullest productivity in verification utilising SystemVerilog and UVM with fully independent specialist training from Doulos subject matter experts.

Check out more details here

Doulos has also released a summary of UVM supported by introductory free technical resources on its website; check them out here

Doulos will be publishing the UVM Golden Reference Guide later in 2010. You can register your interest to receive notification when it becomes available. (Please note this has now expired).

Doulos brings system-on-chip and field programmable gate array design and verification expertise to Xilinx customers in North America

Doulos is proud to announce the extention of its relationship with Xilinx by becoming the Authorized Training Provider for Northern California.

The powerful combination of focused, up-to-date technology training created by Xilinx and best-in-class language and methodology training from Doulos will provide new possibilities for design and verification engineers to get the best performance from their designs and their own efforts. Doulos provides a one stop shop for essential knowledge and skills covering detailed technology facts and techniques to systems level modeling and verification methodologies across hardware and embedded software domains. The opportunities for engineering teams to improve performance through effective, integrated training programmes have never been so good.

“Doulos has an excellent track record in delivering high-quality training services to Xilinx customers, working hand-in-hand with our worldwide sales organization,” said Jason Fegley, Training Manager at Xilinx. See full press release for more details.

Doulos & Feabhas announce global partnership in Embedded Software training
Doulos and Feabhas, established leaders in the hardware and software domains respectively for high quality training solutions in electronic system design, are pleased to announce a strategic partnership to provide integrated training solutions for both the hardware and software requirements of deeply embedded system design. The co-operation will deliver the broadest independent training portfolio for electronics system design available globally. Paul Elbro, ARM VP says '..Great news for end-user community for ARM'. Full press release here.
As a result the following training programs are available immediately within the Doulos portfolio across North America and Europe:
Also come and meet ARM and embedded software experts from Doulos and Feabhas at the Doulos pod in the ARM Pavilion at the Embedded Systems Conference San Jose Apr 26-29
Doulos announces 'Get Smart' training for Actel's SmartFusion™ Mixed Signal FPGAs at Embedded World Nuernberg 2010
Building on years of experience in design training for Actel's FPGA products as well as for ARM cores, in collaboration with Actel, Doulos has developed a customised training program to address the needs of developers using SmartFusion mixed signal FPGAs.

Actel's Sr. Manager, Design Solutions Marketing and Training Wendy Lockhart, comments on the partnership with Doulos, "We are happy to have Doulos as a very competent and highly qualified training and support partner for SmartFusion. It will help our customers very quickly adopt this new and exciting technology to considerably shorten their time-to-market."

Go to www.doulos.com/actel to find out more..
Doulos at Embedded World 2010, Nuernberg
Doulos will be presenting two papers on ARM Cortex technology at the Embedded World Conference in Nuernberg, Germany, 2-4 March 2010. You can check out the details here:

Paper: The quickest way to develop your ARM Cortex-M based product
Paper: Using ARM Advanced SIMD (NEON) from C with vectorizing compiler
Please note these links have now expired.
Enhance Your KnowHow with Doulos at DVCon!

(Please note the following links have now expired)

Doulos have a strong presence at DVCon in San Jose, February 22-25, participating in two half-day tutorials and three regular papers. Check out the details below:

Tutorial - Advanced Verification Techniques Using VMM. Doug Smith of Doulos leads a great team of experts presenting an in-depth tutorial which includes real-world examples of best-practice VMM usage. Attendees will get the know-how needed to begin using the latest features in their own projects.
Tutorial 1 (Session 20); Monday February 22, 1.30 - 5.00pm

Tutorial - The OSCI TLM-2.0 Standard and Synthesis Subset. John Aynsley Doulos CTO, Michael Meredith of Forte Design Systems and Michael McNamara of Cadence explore the lessons learned from the practical adoption of the TLM-2.0 standard, the resulting resurgence of SystemC synthesis, and the synergy between the two
Tutorial 2 (Session 21); Monday February 22, 1:30 - 5:00pm

Paper - SystemVerilog Meets C++: Re-use of Existing C/C++ Models Just Got Easier.
Presenter: John Aynsley
Session 4.1; Wednesday February 24, 11.00am - 12.30pm

Paper - Asynchronous Behaviors Meet Their Match with SystemVerilog Assertions
Presenter: Doug Smith
Session 11.2; Thursday February 25, 1.30 - 3.00pm

Paper - Functional Coverage - without SystemVerilog!
Presenter: Doug Smith
Session 13.1; Thursday February 25, 1.30 - 3.00pm

Conference Home Page
NEW Full Edition of the VMM Golden Reference Guide published
VMM GRG cover Further underlining our marketing leading credentials for the development and delivery of SystemVerilog training, Doulos is publishing the full edition of the new VMM Golden Reference Guide (GRG) at DVCon 2010. Check out the full range here
Doulos have worked closely with Synopsys to ensure the VMM GRG fully supports the recent release of VMM 1.2.
Synopsys are sponsoring a FREE copy of the VMM GRG to each attendee pre-registering for the Doulos sponsored Tutorial 1 Advanced Verification Techniques Using VMM 1.2. Register here NOW to get your own copy secured
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