Friday 7 August 2020

Developing & Delivering KnowHow

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Doulos delivers award winning paper at SNUG 09, San Jose
Did you miss SNUG San Jose? Well, you don't need to miss out on the award winning SystemVerilog paper delivered by Doulos "Using Bind for Class-Based Testbench Reuse with Mixed-Language Designs" is available for download in KnowHow, the free technical resources section of the website. More >>
Global goes local !
Inspite of the economic down turn - or maybe because of it, increasing demand for Doulos FPGA training has resulted in new local public class schedules for Comprehensive VHDL and Expert VHDL in Denmark (Herlev, near Copenhagen) and Norway (Oslo). Engineers in increasingly competitive product markets, operating with shrinking design teams, are turning to productivity enhancing training solutions as the quickest and most cost effective way of making limited resources go further - and of addressing the problems created by low level design skills that simply can't be hidden in the current business climate. Doulos is proud to be working in partnership with Silica and Abelia to schedule further public classes in these localities. To view training dates please visit our global course schedule >>
Doulos contributes ARM content to embedded systems book
Doulos has demonstrated its ARM expertise as guest authors of the popular embedded systems book 'C und C++ für Embedded Systems,' contributing the first German language introduction to ARM Cortex-M3 Architecture. The book provides practical examples, one of which Doulos has delivered and is available for free download in the ARM KnowHow section of the website. More>>
Doulos launches OVM 2.0 Golden Reference Guide - out now!
Just weeks after the official release of OVM 2.0, Doulos has published the brand new, and much anticipated, OVM Golden Reference Guide. Fully supporting OVM 2.0, this new addition to the popular GRG series, complements the OVM User Guide, and underlines Doulos' market leading credentials in the development and delivery of up-to-the-minute SystemVerilog Training. Read more and buy online »
New SystemC TLM-2.0 training announced
The new 3-day 'SystemC Modeling using TLM-2.0' class gives delegates the unique opportunity to hear the features of TLM-2.0 explained by people who worked at the heart of the OSCI standard development. Authorative and comprehensive, it forms the third step of the Doulos 3-step learning Path for effective SystemC use. More >>
Professional FPGA Designer Programme addresses critical design needs
Altera or Xilinx devices and tools now have a much needed answer to their design problems. Altera Professional Designer™ and Xilinx Professional Designer™ programmes provide the best combination of HDL, design flow and techncial training modules. Engineers and their managers can now optimise time invested in training and achieve ellusive design performance goals. Find out more about individual classes here >>

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