Doulos Principal Member of Technical Staff Dr David Long will be presenting Verification Methodologies for Next Generation Designs, a one-day workshop in Bangalore on November 23rd.
Doulos is taking part in "Verification Futures", a series of free 1 day conferences taking place across Europe in November, organised by verification specialists (and Doulos Certified Training Partner) Test and Verification Solutions.
Doulos CTO John Aynsley will also be presenting UVM: Now or Never, in Windsor on 19th and Munich on 22nd November.
Doulos is pleased to be sponsoring the following events in Europe this October organised by Mentor Graphics.
Doulos are pleased to announce three webinars this Autumn as part of their on-going commitment to providing high value, cutting edge KnowHow resources:
Find out about the current on-line training schedule and register »
Following the announcement this week by Accellera of version 2.3.0 of its SystemC library, Senior Member of Technical Staff at Doulos, David Black, who chairs the Accellera Systems Initiative Language Working Group, has been talking about the release to Editor of EDA Confidential, Peggy Aycinena.
"Accellera Systems Initiative encourages SystemC users and tool suppliers everywhere to move to the new IEEE 1666 standard," said David. "I would like to recognize the members of the SystemC Language Working Group, which is composed of system and semiconductor engineers, vendors and educators worldwide. We appreciate their contribution to the electronic design community and their diligent work in making this new library possible."
See the full article here:
Also see the official library release details at:
ARM Systems Design and Development Conference
Doulos are pleased to be participating this year in the ARM Systems Design and Development Conference organised by DESIGN & ELEKTRONIK at the Kempinski Hotel Airport in Munich.
Don't miss Doulos' ARM guru, Marcus Harnisch, who will be presenting: CMSIS turn 3.0 at 2.30pm (Session 3) on Wednesday July 11.
Entry to the exhibition is free.
Doulos is pleased to announce that, starting this August, a schedule of leading edge professional training classes will be offered in Bangalore from its extensive and renowned portfolio.
"The high calibre engineers that form the Indian VLSI design community can now benefit from local access to the Doulos high capability training," said Rob Hurley, CEO Doulos, "we plan to play a key part in the drive to increase engineering productivity in India as elsewhere."
Offered in co-operation with verification specialists Test and Verification Solutions India Pvt Ltd, the first classes offered will deliver project ready skills and expert knowhow in SystemVerilog/UVM, the latest ARM Cores, and system level modelling using SystemC and TLM-2.0.
Karthik Nagappan of Test and Verification Solutions commented, "The program of Doulos training will further accelerate the local strength of engineering competence in VLSI design especially in the key domain of verification. We're excited to be partnering Doulos in this initiative."
For fuller details check out www.doulos.com/india
SPECIAL LAUNCH PROMOTION: Synopsys users attending SNUG Bangalore will be given the chance to win a free training place by registering at the Doulos booth. All SNUG attendees will be eligible for an introductory discount.
Doulos is delighted to be providing Silver Sponsorship for SNUG events in 2012.
Visit the Doulos booth or contact the sales team directly to find out more.
A lunch and learn workshop: "UVM: Now or Never?" will be presented on Wednesday 6.
There will also be opportunities for one-on-one consultations at Booth #1501 with Doulos industry experts John Aynsley, David Black and Doug Smith for managers reviewing their engineering team's technology and methodology capability.