Doulos announces upgrade to SystemVerilog portfolioDoulos is pleased to announce a significant revision and updates to its established SystemVerilog portfolio at DVCon 2013 in San Jose.
Since its inception the spectrum of application and utility for SystemVerilog has developed significantly. In line with the demands for finely tuned training programs for application to both design and verification contexts, Doulos has led the market in providing 'fit for purpose' training programs that have rightly been referenced by customers in all parts of the industry.
In its 10th year of delivering SystemVerilog training, Doulos is announcing the results of a major revision which includes some new advanced materials on UVM and new in-depth course programs for SystemVerilog & UVM practitioners.
This program will be available from May 2013
- NEW: Intensive SystemVerilog & UVM
Accelerated program for verification teams delivered in an intensive productive format
- ENHANCED: UVM Adopter Class
Now 4 days of in-depth content to ensure most complete ready-to-go preparation for real-life UVM projects
- NEW: SystemVerilog Primer Class
Flexible access to foundational knowledge for SystemVerilog application
- REVISED: Comprehensive SystemVerilog
Updated with current best practice - now scheduled globally in 10 locations covering North America, Europe and India
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