Monday 19 February 2018

Developing & Delivering KnowHow

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RapidGain™ - Optimizing Performance for Altera

Duration - 1 day

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RapidGain™ Optimizing Performance for Altera provides an exceptional opportunity to learn about key advanced features of the Quartus® II software that enable design optimization - all in a single day. You will learn the basics of how to optimize designs for timing, area and power using Quartus II's TimeQuest Timing Analyzer, the Incremental Compilation flow and PowerPlay power analysis. Tightly focused and practical, this one-day hands-on training event will show existing users how to get the most from the Quartus II tools. You will:

  • Understand how and why to use TimeQuest in a Quartus II project
  • Learn to write timing constraints using the industry-standard SDC language
  • See how Incremental Compilation can help you to improve your productivity
  • Learn how PowerPlay can help you analyze and optimize the power consumption of your FPGA designs

RapidGain™ - Optimizing Performance for Altera is not available for
in-house delivery.
Doulos is an Approved Altera Training Provider

Who should attend?

  • Existing users of Quartus II and Altera FPGAs


This is not an introductory course. Prior experience of Quartus II and Altera FPGAs is required. Ideally, you should have some knowledge of VHDL or Verilog. You should have a basic understanding of digital logic design, and be computer-literate.

Structure and content

Timing Verification using TimeQuest

The TimeQuest GUI • Timing analysis basics • Slow- and fast-corner timing models • How to constrain the design • How to create and edit SDC files • False paths and clock domain crossing • Timing reports
LAB: Creating an SDC file and running static timing analysis

Improving Designs with Incremental Compilation Flow

Set up and perform incremental compilation • Top-down design flow • Bottom-up design flow • How Incremental Compilation Works • Floorplan and LogicLock regions • Design partitions • Virtual Pins • Team-Based Design
LAB: Practice incremental compilation methodology

Running power analysis with PowerPlay

Power Challenges • Power Basics in FPGAs • Techniques for reducing power • Quartus II PowerPlay Early Power Estimation • PowerPlay Power Inputs • Typical Power Analysis Methods
LAB Running a power analysis based on a gate level simulation

Where do I go from here?

Summary and conclusions • Doulos Altera training roadmap

Looking for team-based training, or other locations?

Complete an on-line form and a Doulos representative will get back to you »

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