Tuesday 16 October 2018

Developing & Delivering KnowHow

Home > Training > RapidGain - Effective Timing Analysis Using Altera TimeQuest

RapidGain™ - Effective Timing Analysis Using Altera TimeQuest

Duration - 1 day

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Timing constraints and analysis are instrumental to the success of your FPGA development. A strong understanding of the techniques can help you meet timing closure, successfully interface to high performance I/O, and reduce your development time.

RapidGain - Effective Timing Analysis Using Altera TimeQuest is not available for in-house delivery.

Attend and you will..

  • Understand how and why to use TimeQuest in a Quartus® II project
  • Learn how to write timing constraints using the industry-standard SDC language
  • Know how to run timing analysis and enhanced reporting
  • Learn how to constrain and report SDR and DDR interfaces

In just 1-day, the RapidGainTM class enables fast, effective assimilation of knowledge and experience through a combination of hands-on experience and focused tuition. Accessible to even the most time constrained or budget restricted engineeers, RapidGainTM Effective Timing Analysis Using Altera TimeQuest delivers exceptional value and immediate benefits.

Who should attend?

Existing users of Quartus II and Altera® FPGAs . This is not an introductory class. Prior experience of Quartus II and Altera FPGAs is required. Ideally, you should have some knowledge of VHDL or Verilog.

Content

Timing Verification using TimeQuest

TimeQuest basics • Timing analysis basics • How does timing verification work? • The TimeQuest GUI • Basic steps to run a timing analysis • Creation and update of the timing netlist • Launch and latch edges • Setup & hold times • Setup and hold slack analysis
LAB:Introduction to theTimeQuest Tool

Timing reports and constraints

Reporting in Quartus II compilation Report • Reporting in TimeQuest TA • Summary report • advanced reporting • Importance of constraining • SDC timing constraints • Base clocks and generated clocks • Clock Latency • Clock Uncertainty • Altera non standard sdc commands
LAB: Clock Constraints

More on Timing constraints

I/O timing • Input/Output delays • Synchronous I/O example • Clock groups • False paths • Multicycle paths • DDR reporting • Example applications
LAB: Synchronous I/O Constraints
LAB: Timing Exceptions & Analysis

Where do I go from here?

Summary and conclusions • Doulos training roadmap for Altera users

Looking for team-based training, or other locations?

Complete an on-line form and a Doulos representative will get back to you »


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