Saturday 11 July 2020

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RapidGain™ VHDL Using Microsemi

Duration - 1 day

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RapidGain™ VHDL Using Microsemi is unique in offering delegates an introduction to VHDL with hands-on exercises using Microsemi software for developing Flash-based FPGAs in a single day!

Delegates will rapidly gain an understanding of the tools and processes involved in creating an FPGA design, achieving significant initial productivity gains.

Who should attend?

  • Digital designers thinking about making the first moves to VHDL and FPGA design
  • Managers who want to understand more about the process of creating FPGA designs and VHDL
  • Analogue or Systems designers who work with digital design teams


No prior experience of VHDL or Microsemi FPGAs and software is needed. You should have a basic understanding of digital logic design, and be computer-literate.

Structure and content

Getting Started with VHDL

What is an FPGA? • What is VHDL? • Tools for FPGA design • How does VHDL affect my design style? • Design flow • Design entity • Ports • Signals • STD_LOGIC • Signal assignment • Processes • Hierarchy • Testbenches • Simulation with ModelSim
LAB: Simulating a binary counter, using ModelSim

Using the LiberoSoC Software

LiberoSoC software • Creating a project • Specifying pin assignment constraints • Setting up timing constraints and generating timing reports • Implementing a design using the LiberoSoC software • Gate-level simulation
LAB: Implementing counter using LiberoSoC, and programming a development board

Writing VHDL for Synthesis

Summary of VHDL constructs and their synthesis • Creating finite state machines Synchronous and Asynchronous controls • The NUMERIC_STD package
LAB Modifying the counter, re-implement and re-program the FPGA

Where do I go from here?

Summary and conclusions • Doulos VHDL, and FPGA training roadmap


Please contact Doulos to find out about the next RapidGain™ event or to discuss other options for RapidGain™ training »

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