Intel - Arm SoC FPGA design
(formerly Altera - Arm SoC FPGA design)
Standard Level - 2 daysview dates and locations
This course is intended for hardware and software engineers providing guidance on implementing an Intel® SoC with the Arm® Cortex®-A9 hard processing system (HPS).
Day 1 will leverage your knowledge of Qsys system design and focus on the hardware aspects of using the processor in the SoC from the design, verification and debug hardware perspectives just as if the processor was external. The intention is that you feel completely comfortable using the HPS in the SoC and know all of the resources at your disposal to work with the board designer, FPGA engineer, firmware engineer or software engineer to get up and running quickly.
On the second day of the course you will learn about software bringup and development on the embedded Arm Cortex-A9 hard processor system (HPS) in an SoC. The course isn't intended to teach you software application or driver development, but rather concentrates on the unique aspects of the embedded HPS software flow in an SoC. You'll learn everything you need to know to get started developing our software for the HPS component right away, where to go to get help, as well as how to use the Intel® edition of the Arm DS-5 adaptive debugging tools at your disposal to debug your software.
- Some basic software knowledge and C/C++ coding skills are required.
- Experience of the QSys System Integration Tool
- FPGA knowledge is not required, but a plus.
- The Intel SoC FPGA families with Arm Cortex A9 MP Embedded Processing units
Dichitomy Logic Programmable (User Logic) - HPS (Hard Processor System). Pin-assignment and pin-sharing issues. Rapid introduction to the HPS System blocks (processors, integrated peripherals, Memory Interfaces, Caches and provisions for data integrity and debugging, interconnects and data flow...).
- Configuring the HPS
Clocking, Reset, Configuration source, Boot sources, configuring the bridges with the Programmable (User) side.
Practical Exercise: Creating a complete project and Configuring the HPS.
- Building the Communication between HPS and Configurable (User) Logic
Reviewing and understanding the different links available, and how/when to use them. Mapping User Peripherals in the HPS memory map. Accessing HPS peripherals from the User Logic side.
Practical Exercise: Golden Hardware Reference Design including a User Peripheral for Digital Signal processing on a stream of data.
- Introduction to SystemVerilog BFMs and to the verification environment
- Hardware to Software Handoff
Principles, tools and files involved. Understanding all the start up phases (from the initial configuration to the working Operating System Linux) with the possible options and boot sources.
- SoCAL and HWLIB
Current situation and roadmap. Limitation of bare-metal. AMP vs SMP.
- The BSP Editor
- The Arm Development Environment : DS-5
General functions, code entry, compilation, connection and download to the target. Avoiding pitfalls.
- Understanding the Preloader and the tasks it implements
Practical Exercise: generating the preloader, code inspection, inserting user code and bare-metal debug using DS-5.
- Combined Hardware-Software debugging
Practical Exercise:Adaptative Debugging and Cross-triggering.
- Presenting the available Embedded Operating Systems
The Linux distribution proposed and maintained by Intel (Altera).
- Using Streamline tools for Real-time Monitoring and Analysis
|April 7th, 2020||Ringwood, UK||Enquire|
|May 13th, 2020||Munich, DE||Enquire|
|September 16th, 2020||Ringwood, UK||Enquire|
|indicates CONFIRMED TO RUN courses.|
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