Embedded Design for Intel SoC FPGAs
(formerly Altera SoC FPGAs)
Standard and Advanced Level - 4 days
The latest Intel® SoC FPGAs (Altera® Cyclone® V & Arria® V), with their Embedded Processing System using ARM® Cortex®-A9 MPCores represent a significant evolution for Altera devices. To help you understand the design challenges and maximise the potential of these SoC FPGAs, this modular four day training course, covers the essential concepts and tools usage to help you start a new application with confidence, as well as provide lots of practical examples that you can use as a basis within your environment.
The first day focuses on Qsys and how to build, populate and verify the FPGA (hardware programmable) side of the device.
The two following days must be attended together: they cover the Hardware then the Software aspects of the SoC FPGAs.
The final day is dedicated to the Embedded Linux distribution, developed and maintained by Altera. This day is recommended for both Linux novices and experienced designers, in both software and hardware contexts, as bare metal is not the recommended path.
Who should attend?
Hardware and software engineers who wish to learn how to design and program the Altera SoC FPGAs.
- Not sure how much training you need?
- Looking to attend specific modules?
- Part of a team?
Attendence of specific modules is possible, depending on your experience, and on-site training is also available to optimize the course to your precise needs, experience, and expectations.
Please contact your local Doulos team to discuss your requirements.
- A strong interest in using the Altera SoC FPGAs
- Basic understanding of Digital Design and Programmable Logic
- If possible: an ability to understand simple C code
What will you learn?
- How to use Qsys to build a custom computing platform with Master and Slave Peripherals.
- How a Nios II softcore can be added to exercise and debug this system.
- How to activate, configure, program and debug the HPS Side (Embedded Cores and peripherals), both Software and Hardware aspects.
- How to set up, configure and use the Altera Linux distribution, also in the context of driving custom peripherals.
Course Content - Details
Enquire now to book for the full training course, or please select the module(s) you require from the learning path or links above. Not sure what you need? Use the Altera Embedded Design Learning Path above to help you decide or read on to see full details of the content.
Appropriate topics are followed by practical hands-on exercises.
Part 1: Using Qsys to build the Custom Logic
- Basic concepts
Introduction to Altera SoPC. The Interconnect Fabric and its generation using Qsys. The Nios II processors. Standard Peripherals (SystemID, Jtag UART, On-chip memory, PIO, Timer...).
- Introduction to Qsys
Practical Exercise: Create a complete SoPC system and test on the SoCKit.
- Introduction to Custom Peripherals and using SystemConsole
High Value of custom peripherals. Avalon bus formats : ST & MM. The Component Editor. Creating & publishing a custom peripheral. Principle and basic use of SystemConsole for System Bring up.
Practical Exercise: Using VHDL to design a Custom peripheral, tested on the SoCKit.
- Introduction to Nios II EDS / Eclipse Software Development Environment
Creating a Software Project. Entering and compiling the code. Loading, executing and debugging the code under Eclipse.
Practical Exercise: Creating a software project using the custom Peripheral tested on the SoCKit
- Validating the hardware platform by HDL (co)simulation.
Creating the simulation models, behavioral models and BFMs, using ModelSim.
Practical Exercise: RTL Simulation of the SoPC system using ModelSim AE.
Part 2: Intel ARM SoC FPGA Design (2 days)
- The SoC FPGA Altera families with ARM Cortex A9 MP Embedded Processing units.
Dichitomy Logic Programmable (User Logic) - HPS (Hard Processor System). Pin-assignment and pin-sharing issues. Rapid introduction to the HPS System blocks (processors, integrated peripherals, Memory Interfaces, Caches and provisions for data integrity and debugging, interconnects and data flow...).
- Configuring the HPS
Clocking, Reset, Configuration source, Boot sources, configuring the bridges with the Programmable (User) side.
Practical Exercise: Creating a complete project and Configuring the HPS.
- Building the Communication between HPS and Configurable (User) Logic.
Reviewing and understanding the different links available, and how/when to use them. Mapping User Peripherals in the HPS memory map. Accessing HPS peripherals from the User Logic side.
Practical Exercise: Golden Hardware Reference Design including a User Peripheral for Digital Signal processing on a stream of data.
- Introduction to SystemVerilog BFMs and to the verification environment.
- Hardware to Software Handoff
Principles, tools and files involved. Understanding all the start up phases (from the initial configuration to the working Operating System Linux) with the possible options and boot sources.
- SoCAL and HWLIB
Current situation and roadmap. Limitation of bare-metal. AMP vs SMP.
- The BSP Editor
- The ARM Development Environment : DS-5
General functions, code entry, compilation, connection and download to the target. Avoiding pitfalls.
- Understanding the Preloader and the tasks it implements.
Practical Exercise: generating the preloader, code inspection, inserting user code and bare-metal debug using DS-5.
- Combined Hardware-Software debugging
Practical Exercise:Adaptative Debugging and Cross-triggering.
- Presenting the available Embedded Operating Systems
The Linux distribution proposed and maintained by Altera.
- Using Streamline tools for Real-time Monitoring and Analysis
Part 3: Embedded Linux for SoC FPGAs
- What is Embedded Linux?
Principles and Jargon.
- Rapid Description of the Altera distribution
Yocto (and Ängström) : why and for whom. Demo: customizing the standard distribution.
Practical Exercise: How to build the Linux Image, program the SD-Card and boot Linux using DS-5.
- The main Linux shell commands and services
Practical Exercise: Experimenting with the Altera distribution on the SoCkit. Boot, command line (shell), services, connection to the Ethernet, volume mounting, etc
Practical Exercise: booting from a network, image.
- The Device Tree Generator
How to dynamically take user (custom) peripherals located in the programmable side into account.
Practical Exercise: creating and testing a simple driver for the custom DSP processing peripheral.
- Software Cross-Development
Coding, compiling, executing and debugging a Linux Application with user peripherals. Practical Exercise: using the previously developed driver in an application.
|December 2nd, 2019||Ringwood, UK||Enquire|
|April 6th, 2020||Ringwood, UK||Enquire|
|May 12th, 2020||Munich, DE||Enquire|
|indicates CONFIRMED TO RUN courses.|
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