Arm Cortex-A53/A57/A72 MPCore Software Design
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Duration: 3 daysview dates and locations for In-Person training
This course covers the Arm® Cortex®-A53/A57/A72 architecture and programmer's model knowledge required for those developing software for platforms powered by Armv8 processors.
Who should attend?
Software engineers designing bare metal or driver level applications for platforms powered by the Arm Cortex-A53/A57/A72 MPCore application processors.
Knowledge of earlier Arm architectures such as Arm v6/7 is a necessity as this course mainly focusses on the AARch64 aspect of the v8 architecture.
Delegates should also have some knowledge of embedded systems, and a basic understanding of embedded programming in C and assembler.
This class uses training materials developed by Arm®
- Introduction to Armv8-A Architecture versions • Privilege levels • AArch64 registers • A64 Instruction set • AArch64 Exception model • AArch64 memory model
- Cortex-A57/A53/A72 Processor Overview Cortex-A57/A53/A72 introduction • New features in Cortex-A57/A53/72
- AArch64 A64 ISA Overview Register set • Load/store instructions • Data processing instructions • Program flow instructions • System control • Advanced SIMD • Cryptographic extensions
- AArch64 Exception Model The AArch64 exception model • Interrupts • Synchronous exceptions • SError exceptions • Exceptions in EL2 and EL3
- Armv8-A Memory Management Memory management theory • Stage 1 translations at EL 1/0 • Kernel/application space translation tables • Translations at EL2/EL3 • Stage1 tables for hypervisor/secure exception levels • Stage2 tables for virtualized systems • TLB maintenance
- Armv8-A Memory Model Memory types • Memory attributes • Memory alignment and endianess
- Caches and Branch Prediction General cache information • Cache attributes • Cache maintenance operations • Cache discovery
- Barriers Data barriers • Instruction barriers
- Synchronization Synchronization implementation • Local exclusive monitors • Global exclusive monitors
- Cache Coherency Introduction to coherency • Coherency details for multi core processors • Coherency details for multi processor systems
- OS Support Context switching • Modifying translation tables • Privilege escalation protections • Timers
- Software Engineer's Guide to the Cortex-A57/A53/A72 Core overview • Configuration options • Pipeline • Cache logic and branch prediction • Memory management • Interrupts and bus interfaces • Debug features • Power management
- Booting Booting a cortex-A53/57 processor in AArch64 • Processor setup
- Virtualization What is virtualization • Arm virtualization support • Memory Management • Exception Handling • Introduction to SMMU
- Security Software stack • Memory system • Debug • TBSA
- GIC Programming Distributor and CPU Interfaces • How to enable and configure interrupts • How to handle interrupts • How to send software interrupts • Security Extensions
- Debug Debug infrastructure • Invasive debug • Non invasive debug
- Power management for Cortex-A Power Overview • Processor Power Modes • Multiprocessor and System Power Modes • Cortex-A Power Modes
- Software Engineer's guide to system fabric Interrupt controller • System MMU • TrustZone Address Space Controller • Generic Timer
The learning is reinforced with unique Lab Exercises using Arm DS-5 instruction set simulators and covering assembly programming, exception handling and setting up the caches and MMU.
Lab exercises for assembly programming cover the concepts of data processing, flow control, and rely on the development tool-set offered by Arm DS-5.
Exception handling lab exercises look at setting up various execption levels vector table and execution modes as well as executing hypervisor and secure calls.
The Memory management lab takes you though the steps involved in implementing a typical system memory configuration using the MMU.
|December 7th, 2020||Munich, DE||Enquire|
|December 14th, 2020||Ringwood, UK||Enquire|
|indicates CONFIRMED TO RUN courses.|
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