Standard Level - 5 sessionsview dates and locations
PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE.
It covers the same scope and content as a scheduled face-to face class and delivers comparable learning outcomes. Daily sessions comprise 4-6 hours of class contact time.
This course covers software aspects of designing with an Arm® Cortex®-A53/A57 MPCore based device, highlighting the core architecture details and the programmer's model. Topics include the Arm AArch64 exceptions model, details of the available caching schemes and coherency management, memory management and the Arm memory model. Additionally the sections on the v8 architecture instruction set and steps involved in initializing an MPCore system deliver the essential knowledge required for programming and debugging a Cortex-A53/57 MPCore processor.
Hands-on LabsThe learning is reinforced with unique Lab exercises using Arm DS-5 instruction set simulators and covering assembly programming, exception handling and setting up caches and MMU.
FormatThe format of Live ONLINE training from Doulos is focused on delivery of a single 4 hour intensive session per day. This includes live tuition and class interaction with the Doulos subject matter expert during the full scope of each session.
Due to the heavy lecture content of this class, Labs are provided as additional homework. These are done with the Doulos lab platform providing individuals, instant access to a pre-configured working environment.
Who should attend?
- Engineers who wish to become skilled in the use of a Cortex-A53/57 based System On Chip from a software development and verification perspective.
- Engineers who will required to provide a software solution to bring a bare metal Cortex-A53/57 MPCore system to life.
- Engineers who need to implement an operating system running on an Arm v8 processor.
What will you learn?
- AArch64 execution state fundamentals
- The details of a Cortex-A53/57 processor core
- The details of the MPCore logic
- Memory management for Arm v8 based devices
- Bare metal system bring-up
Pre-requisitesKnowledge of earlier Arm architectures such as Arm v6/7 is a necessity as this course mainly focusses on the AARch64 aspect of the v8 architecture.
Delegates should also have some knowledge of embedded systems, and a basic understanding of embedded programming in C and assembler.
The source training materials are provided under license form Arm. This material has been purposely crafted to accomodate the online delivery format.
- Introduction to Armv8-A Architecture versions • Privilege levels • AArch64 registers • A64 Instruction set • AArch64 Exception model • AArch64 memory model
- AArch64 A64 ISA Overview Register set • Load/store instructions • Data processing instructions • Program flow instructions • System control • Advanced SIMD • Cryptographic extensions
- AArch64 Exception Model The AArch64 exception model • Interrupts • Synchronous exceptions • SError exceptions • Exceptions in EL2 and EL3
- Armv8-A Memory Management Memory management theory • Stage 1 translations at EL 1/0 • Kernel/application space translation tables • Translations at EL2/EL3 • Stage1 tables for hypervisor/secure exception levels • Stage2 tables for virtualized systems • TLB maintenance
- Armv8-A Memory Model Memory types • Memory attributes • Memory alignment and endianess
- Caches and Branch Prediction General cache information • Cache attributes • Cache maintenance operations • Cache discovery
- Barriers Data barriers • Instruction barriers
- Synchronization Synchronization implementation • Local exclusive monitors • Global exclusive monitors
- Software Engineer's Guide to the Cortex-A57/A53 Core overview • Configuration options • Pipeline • Cache logic and branch prediction • Memory management • Interrupts and bus interfaces • Debug features • Power management
- Booting Booting a cortex-A53/57 processor in AArch64 • Processor setup
- Power management for Cortex-A Power Overview • Processor Power Modes • Multiprocessor and System Power Modes • Cortex-A Power Modes •
- Virtualization What is virtualization • Arm virtualization support • Memory Management • Exception Handling • Introduction to SMMU
- Security Software stack • Memory system • Debug • TBSA
- GIC Programming Distributor and CPU Interfaces • How to enable and configure interrupts • How to handle interrupts • How to send software interrupts • Security Extensions
- Debug Debug infrastructure • Invasive debug • Non invasive debug
The learning is reinforced with unique Lab Exercises using Arm DS-5 instruction set simulators and covering assembly programming, exception handling and setting up the caches and MMU.
Lab exercises for assembly programming cover the concepts of data processing, flow control, and rely on the development tool-set offered by Arm DS-5.
Exception handling lab exercises look at setting up various execption levels vector table and execution modes as well as executing hypervisor and secure calls.
The Memory management lab takes you though the steps involved in implementing a typical system memory configuration using the MMU.
|May 18th, 2020||ONLINE EurAsia||Enquire|
|June 1st, 2020||ONLINE Americas||Enquire|
|December 7th, 2020||ONLINE EurAsia||Enquire|
|indicates CONFIRMED TO RUN courses.|
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