Tuesday 7 July 2020

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Arm Cortex-A53 MPCore SoC Design

Duration: 3 days

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This course is designed for those who are designing hardware based around the Arm® Cortex®-A53 MPCore processors. It includes a one-day introductory course on the Armv8-A architecture and AMBA.

Who should attend?

Hardware design engineers who need to understand the issues involved when designing SoCs around the Arm Cortex-A53 MPCore processor.


  • Knowledge of embedded systems
  • Experience with digital logic and hardware/ASIC design issues

Training materials

This class uses training materials developed by Arm®


  • Cortex-A53 MPCore Overview
  • Cortex-A53 CPU Core
  • Cortex-A53 MPCore Memory Subsystems
  • Cortex-A5x MPCore MMU
  • CCI-400 Cache Coherent Interconnect (or CCN-504 Cache Coherent Network)
  • Cortex-A5x Generic Interrupt Controller
  • Cortex-A53 MPCore Clock & Resets
  • Cortex-A53 MPCore Power Management
  • Cortex-A53 MPCore Debug
  • Cortex-A53 MPCore Configuration
  • Cortex-A5x MPCore Booting
  • Cortex-A53 MPCore Implementation & DFT
  • Cortex-A53 MPCore Integration

Looking for team-based training, or other locations?

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