Arm Cortex-A53 for Zynq UltraScale+ MPSoC
Duration: 4 days
This course covers the software aspects of designing with an Arm® Cortex®-A53 MPCore based device, highlighting the core architecture details and the Xilinx® Zynq® UltraScale+™ implementation choices. Topics include the AArch32 and AArch64 programmer's model, Arm v8-A exceptions' model, details of the available caching schemes and coherency management, memory management and the Arm memory model. Additionally, the Arm assembly section delivers the essential knowledge required for programing and debugging with T32, A32 and A64 assembly languages.
Although this training class covers both the AArch32 and AArch64 execution states implemented by the Arm v8-A architecture, a strong emphasis is put on the latest AArch64 implementation.
For teams designing applications that utilise the real-time R5 processor within the UltraScale+ MPSoC, a custom onsite training program can be delivered incorporating additional content from the Arm Cortex-R5 Software Design course.
- Custom onsite courses are available worldwide.
- The extended agenda and training timetable increase the program to a minimum of 5 days duration
- Please speak to a Doulos technical staff member about your application needs via your local Doulos sales office.
The learning is reinforced with unique Lab exercises using the Xilinx Zynq UltraScale+ QEMU virtual platform. It covers assembly programming to bring a complete bare metal system to life as well as writing bare metal device drivers.
Who should attend?
- Engineers who wish to become skilled in the use of an Arm Cortex-A53 based System On Chip from a software and verification perspective
- Engineers who are required to provide a software solution to bring a bare metal Arm Cortex-A53 MPCore system to life.
What will you learn?
- The hardware structure of a Xilinx Zynq UltraScale+ device
- The details of an Arm Cortex-A53 processor core
- The details of the MPCore logic
- Memory management for Arm v8-A based devices
- Assembly programing for the T32/A32/A64 instruction sets
- Bringing up an Arm Cortex-A53 bare metal system
Delegates should have some knowledge of embedded systems and a basic understanding of embedded programming in C and assembler. Knowledge of earlier Arm architectures is an advantage but not required.
C programming for Embedded Systems training is also available from Doulos.
A carefully crafted combination of content from Arm, Xilinx and Doulos will be used to provide exhaustive coverage of all of the essential topics required to achieve the learning objectives.
Training material includes fully indexed course notes creating a complete reference manual.
- Introduction to Xilinx Zynq UltraScale+ Architecture details with Cortex-A53 MPCore implementation choices • Core and FPGA interfaces • Processing System Built-in Peripherals • Memories and Memory Controllers • FPGA logic and rooting details • I/O Peripherals • Cortex-A53 core building blocks • Private peripherals • Snoop control unit • Accelerator coherency Port (ACP) • Generic interrupt controller • Core system interfaces
- Introduction to A32 instruction set Load/Store Instructions • Data Processing Instructions • Flow Control • Miscellaneous • DSP
- AArch32 Exception Handlers for Arm application processors Exceptions overview • Interrupts sources and priorities • Abort Handlers • SVC Handlers • Undef Handlers • Reset Handlers
- AArch32 Memory management Memory management basics • Memory attributes • Virtual to Physical address conversion • AArch32 Short and long descriptors • AArch32 translation granule
- Introduction to Armv8-A Architecture versions • Privilege levels • AArch64 registers • A64 Instruction set • AArch64 Exception model • AArch64 memory model
- Cortex-A53 Processor Overview Cortex-A53 introduction • New features in Cortex-A53
- AArch64 A64 ISA Overview Register set • Load/store instructions • Data processing instructions • Program flow instructions • System control • Advanced SIMD • Cryptographic extensions
- AArch64 Exception Model The AArch64 exception model • Interrupts • Synchronous exceptions • SError exceptions • Exceptions in EL2 and EL3
- Armv8-A Memory Management Memory management theory • Stage 1 translations at EL 1/0 • Kernel/application space translation tables • Translations at EL2/EL3 • Stage 1 tables for hypervisor/secure exception levels • Stage 2 tables for virtualized systems • TLB maintenance
- Armv8-A Memory Model Memory types • Memory attributes • Memory alignment and endianess
- Caches and Branch Prediction General cache information • Cache attributes • Cache maintenance operations • Cache discovery
- Barriers Data barriers • Instruction barriers
- Synchronization Synchronization implementation • Local exclusive monitors • Global exclusive monitors
- Cache Coherency Introduction to coherency • Coherency details for multi core processors • Coherency details for multi processor systems
- Software Engineer's Guide to the Xilinx Zynq UltraScale+ Core overview • Configuration options • Pipeline • Cache logic and branch prediction • Memory management • Interrupts and bus interfaces • Debug features • Power management
- Booting Booting a cortex-A53 processor in AArch64 • Processor setup
- Virtualization What is virtualization • Arm virtualization support • Memory Management • Exception Handling • Introduction to SMMU
- Security Software stack • Memory system • Debug • TBSA
- Debug Coresight debug infrastructure • Invasive versus non-invasive debug • Debug access port • Watchpoints, breakpoint and trace units
The learning is reinforced with unique Lab Exercises using Xilinx QEMU UltraScale+ instruction set simulators and covering assembly programming, exception handling and setting up the caches and MMU.
- Lab exercises for assembly programming cover the concepts of data processing, flow control, and rely on the GNU development tool-set.
- Exception handling lab exercises look at setting up various exception levels vector table and execution modes as well as executing hypervisor and secure calls.
- The Memory management lab takes you though the steps involved in implementing a typical system memory configuration using the MMU.
|May 4th, 2020||Ringwood, UK||Enquire|
|May 19th, 2020||Copenhagen, DK||Enquire|
|May 19th, 2020||Stockholm, SE||Enquire|
|May 26th, 2020||San Jose, CA||Enquire|
|July 7th, 2020||Stockholm, SE||Enquire|
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