Saturday 4 July 2020

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Arm Cortex-A5 MPCore SoC Design

Standard Level - 4 days

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This course is designed for those who are designing hardware based around the Arm® Cortex®-A5 processor.

This is an excellent preparatory course for AAE candidates.

Who should attend?

Hardware design engineers who need to understand the issues involved when designing SoCs around the Arm Cortex-A5.


  • Some knowledge of embedded systems
  • Familiarity with digital logic and hardware/ASIC design issues
  • A basic awareness of Arm is useful but not essential

Training materials

This class uses training materials developed by Arm.


  • Cortex-A5 Overview
  • Arm v7-A Instruction Sets
  • Introduction to TrustZone
  • AXI Protocol
  • AXI Interconnection Architectures
  • PL301/NIC301
  • Cortex-A5 Processor Core
  • Cortex-A5 L1 Sub-Systems
  • Cortex-A5 L2 Interfaces
  • Cortex-A5 Configuration & Deployment
  • Cortex-A5 Reference Methodology Overview
  • Cortex-A5 Clocks, Resets & Power Management
  • Cortex-A5 Memory Management
  • L2C-310 Level 2 Cache Controller
  • Introduction to CoreSight
  • Cortex-A5 Invasive Debug
  • Cortex-A5 Non-Invasive Debug
  • Cortex-A5 Integration

Looking for team-based training, or other locations?

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