Arm Cortex-A7/A15/A17 MPCore Software Design
Duration: 3 daysview dates and locations
This training course is ideal for engineers involved in developing software for platforms powered by the Arm® Cortex®-A7/A15/A17 application processors.
The learning is reinforced with unique Lab exercises (using the Arm DS-5) which cover Memory Management Unit programming, Generic Interrupt Controller programming and Performance Monitoring Unit programming.
Who should attend?
This course is aimed at software developers writing low level and bare-metal code for Armv7-A processors, concentrating on the Cortex-A7/A15/A17 processor.
Delegates must have an existing knowledge of Arm application processors and a basic understanding of embedded programming in C and assembler.
If you do not have a firm understanding of the Arm programmer's model, assembly and exception model, attending the one day Arm fundamentals class is essential.
This class uses training materials developed by Arm®
- Arm Architecture
Architecture version • Registers and instruction sets • Exception model • Memory model • Coprocessors • Architecture extensions • The Future
- Cortex-A7/A15/A17 MPCore Overview
New features in Cortex-A7/A15/A17 • big.LITTLE processing
- Configuring Caches and Branch Prediction
Cache basics • Caches on Arm processors • L2 and L1 Cache interactions • Cache policies • Prefetching and preloading • Optimization consideration
- Using the MMU
MMU Basics • Large Physical Address Extensions (LPAE) • Short-descriptor format • Memory types and attributes • Using the MMU
- Introduction to TrustZone
Exception Handling • Memory System • Debug • Software
- Multi-Processors/Threads Synchronization Atomicity • LDREX/STREX Uses • Mutex Implementation
- Programming the Interrupt Controller (GIC) Distributor and CPU Interfaces • How to enable and configure interrupts • How to handle interrupts • How to send software interrupts • Security Extensions
- Cortex-A Power Management Power Overview • Processor Power Modes • Multiprocessor and System Power Modes • Cortex-A Power Modes
- Maintaining Cache Coherency L1 & L2 cache coherency and maintenance • MPCore coherency
- OS Support Multi-Processing • Translation tables • Context switching • Timers
- Barriers Data barriers • Instruction barriers
- Multi-Cluster Programming Introduction • Multi-Cluster Configurations • Miscellaneous Considerations
- Booting a Cortex-A7/A15/A17 MPCore Overview • Booting a single CPU • Booting a cluster
- Writing C for Arm Parameter passing • Floating point linkage • Alignment • Coding considerations
- NEON Co-Processor Overview NEON Instruction Set Overview • NEON Software Support
- Virtualization in Cortex A-15 Overview of Virtualization Extensions • Memory Management • Exception Handling
- Performance Monitoring Unit and Trace Functionalities Invasive Debug • Non-Invasive Debug • MMU • Trace
The Cortex-A7/A15/A17 MPCore are architecturally (ISA) identical and have been purposely designed to work in tandem in a big.LITTLE configuration whilst relying on automated data cache coherency management. This aspect allows us to provide a consolidated training class covering these processors with minimal redundancy.
The learning is reinforced with practical exercises using the Arm DS-5 software development platform and covers advanced topics such as memory management, interrupt controller and performance monitoring unit configuration. More basic laboratories covering Arm assembly programing and exception handling are covered as part of the one day Arm fundamentals class »
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