Arm Cortex-A9 for FPGA
Standard Level - 3 daysview dates and locations
Doulos offers a specialised training class aimed providing the acute knowledge required for both the software development and system integration of an Arm® Cortex®-A9 based solution. This class is crafted for both a hardware and software engineers audience and structured in three distinct parts. First we introduce the various available Cortex-A9 based FPGA architectures together with the system level aspects of the AXI protocol. The second part details the processor architecture and programmer's model, including the snoop control unit, the general interrupt controller and cache controllers. Lastly we look at the software aspects covering the essentials of both Arm assembler programming and embedded C, going through the steps involved in bringing a bare metal system to life.
Engineers who wish to learn about other features and benefits of technology specific FPGAs beyond the details of the Arm Cortex-A9 processing system may wish to attend our dedicated FPGA system architecture classes.
This class is lectures only.
Who should attend?
- Engineers who wish to become skilled in the use of a Cortex-A9 based System On Chip from a software and verification perspective
- Engineers who need to understand integration details centered around the AXI protocol
- Engineers who will required to provide a software solution to bring a bare metal Cortex-A9 MPCore system to life.
What will you learn?
- The details of a Cortex-A9 processor core
- The details of the MPCore logic
- Memory management for Arm v7 based devices
- AXI system interfaces
- Bringing up a bare metal system
Delegates should have some knowledge of embedded systems, and a basic understanding of embedded programming in C and assembler. Knowledge of earlier Arm architectures is an advantage but not required.
A carefully contextualised selection of material form Arm will be used to provide exhaustive coverage of all of the essential topics required to achieve the learning objectives.
Training material includes:
- Fully indexed course notes creating a complete reference manual
FPGA architecture overview
- Architecture details with Cortex-A9 MPCore implementation choices
- Core and FPGA interfaces
- Processing System Built-in Peripherals
- Memories and Memory Controllers
- FPGA logic and rooting details
- I/O Peripherals
- Processor Boot Options
Introduction to the Cortex-A9 MPCore
- Cortex-A9 core building blocks
- Private peripherals
- Snoop control unit
- Accelerator coherency Port (ACP)
- General interrupt controller
- Core system interfaces
The AMBA AXI bus protocol
- Protocol overview
- Channels, transfers & transactions
- Channel signal
- Transfer behavior
- Transaction ordering
- AXI terminology.
Introduction to Arm assembler programming
- Load/Store Instructions
- Data Processing Instructions
- Data Processing Instructions
- Flow Control
Exception Handlers for Arm application processors
- Exceptions overview
- Interrupts sources and priorities
- Abort Handlers
- SVC Handlers
- Undef Handlers
- Reset Handlers
Caches and Tightly Coupled Memories
- Cache basics
- Caches on Arm processors
- Optimization consideration
- Memory Management Introduction
- Access Permissions and Types
- Memory Management Unit (MMU)
- Optimizations & Issues
- MPCore Features
- Snoop Control Unit
- Accelerator Coherency Port (ACP)
- Interrupt Controller
- Timer and watchdog
- TrustZone Support
- Developing for Arm MPCore Processors
- Booting SMP
- Configuring an interrupt
Embedded software development
- An out-of-the-box” build
- Tailoring the C library to your target
- Tailoring image memory map to your target
- Reset and Initialization
- Further memory map considerations
- Building and debugging your image.
Using the NEON co-processor
- NEON Instruction Set Overview
- NEON Software Support.
Introduction to the TrustZone
- Exception Handling
- Memory System
Looking for team-based training, or other locations?
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