Tuesday 7 July 2020

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Arm Cortex-R4 SoC Design

Standard Level - 4 days

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Arm® Cortex®-R4 SoC Design is a 4-day class for hardware engineers designing systems based around the Arm Cortex-R4 processor core. It includes an introduction to the Arm product range and supporting IP, programmer's model, instruction set architecture, AMBA on-chip bus architecture and the Cortex-R4 debug architecture. The class includes a number of worked examples to reinforce the lecture material.

Who should attend?

Hardware design engineers who need to understand the issues involved when designing SoC's around the Arm Cortex-R4 processor core.


Some knowledge of embedded systems and familiarity with digital logic and hardware/ASIC design issues. A basic awareness of Arm is useful but not essential.

Training materials

This class uses training materials developed by Arm®.


  • The Arm Architecture
  • Arm CPU Architectures
  • Memory Subsystems and Memory Management
  • Cortex-R4 Overview
  • Cortex-R4 Instruction Sets
  • Exception Handling
  • AXI Bus Architecture
  • Primecell Vectored Interrupt Controller
  • Processor Core
  • L1 Subsystems
  • L2 Interfaces
  • Implementation
  • Clocks, Reset and Power Management
  • Arm v6 Memory Types
  • Memory Protection
  • Initialization
  • Interrupts
  • Multiprocessor Synchronization
  • L2 Cache Controller
  • CoreSight Debug Architecture Overview
  • Debug and Trace
  • Arm Processor Simulation Models
  • Integration

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