Thursday 20 September 2018

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ARM Cortex-R5 SoC Design

Standard Level - 4 days

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This course is designed for hardware engineers designing systems based around the ARM Cortex-R5 processor core. Including an introduction to the ARM product range and supporting IP, the course covers the ARM core range, programmer's model, instruction set architecture and AMBA on-chip bus architecture. The Cortex-R5 debug architecture is also covered. The course includes a number of worked examples to reinforce the lecture material.

Who should attend?

Hardware design engineers who need to understand the issues involved when designing SoCs around the ARM Cortex-R5 processor core.

Pre-requisites

Some knowledge of embedded systems and familiarity with digital logic and hardware/ASIC design issues. A basic awareness of ARM is useful but not essential.

Training materials

This class uses training materials developed by ARM®.

Content

  • Introduction
  • Cortex-R5 Overview
  • Memory
  • Cortex-R5 Instruction Sets
  • System Fabric
  • Cortex-R Exception Handling
  • Processor Core
  • L1 Sub-Systems
  • L2 Interfaces
  • Sub-Systems
  • Error Handling Schemes
  • Multi-processor Synchronization
  • Memory Protection Unit
  • Clocks, Resets & Power Management
  • Initialization
  • Debug
  • Introduction to CoreSight
  • Invasive Debug
  • Non-invasive Debug
  • Implementation
  • Integration

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