Arm Cortex-R5 SoC Design
Standard Level - 4 daysview dates and locations
This course is designed for hardware engineers designing systems based around the Arm® Cortex®-R5 processor core. Including an introduction to the Arm product range and supporting IP, the course covers the Arm core range, programmer's model, instruction set architecture and AMBA on-chip bus architecture. The Cortex-R5 debug architecture is also covered. The course includes a number of worked examples to reinforce the lecture material.
Who should attend?
Hardware design engineers who need to understand the issues involved when designing SoCs around the Arm Cortex-R5 processor core.
Some knowledge of embedded systems and familiarity with digital logic and hardware/ASIC design issues. A basic awareness of Arm is useful but not essential.
This class uses training materials developed by Arm®.
- Cortex-R5 Overview
- Cortex-R5 Instruction Sets
- System Fabric
- Cortex-R Exception Handling
- Processor Core
- L1 Sub-Systems
- L2 Interfaces
- Error Handling Schemes
- Multi-processor Synchronization
- Memory Protection Unit
- Clocks, Resets & Power Management
- Introduction to CoreSight
- Invasive Debug
- Non-invasive Debug
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