Tuesday 23 April 2019

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Arm Cortex-R7 Software Design

Doulos Face-to-Face Training

Duration: 3 days

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This course covers developing software for an Arm® Cortex®-R7 MPCore based device, highlighting the core architecture details and programmer's model. Topics include details of the available caching schemes and coherency management, memory management and the Arm memory model. Additionally, the Arm assembly section delivers the essential knowledge required for programming and debugging with T32 (Thumb2), A32 (Arm) assembly languages.

  • Custom onsite courses are available worldwide.
  • Please speak to a Doulos technical staff member about your application needs via your local Doulos sales office.

Hands-on Labs

The learning is reinforced with unique Lab exercises using the QEMU virtual platform. It covers assembly programming to bring a complete bare metal system to life as well as writing bare metal device drivers.

Who should attend?

  • Engineers who wish to become skilled in the use of an Arm Cortex®-R7 based System On Chip from a software and verification perspective
  • Engineers who are required to provide a software solution to bring a bare metal Arm Cortex®-R7 MPCore system to life.

What will you learn?

  • The details of an Arm Cortex®-R7 processor core
  • The details of the MPCore logic and coherency management
  • Memory management for Arm v7-R based devices
  • Assembly programing for the T32/A32 instruction sets
  • Bringing up an Arm Cortex®-R7 bare metal system
  • Writing C/C++ code for Arm processors
  • How to use the compiler and linker efficiently

Pre-requisites

Delegates should have some knowledge of embedded systems and a basic understanding of embedded programming in C and assembler. Knowledge of earlier Arm architectures is an advantage but not required.

C programming for Embedded Systems training is also available from Doulos.

Training materials

A carefully crafted combination of content from Arm and Doulos material will be used to provide exhaustive coverage of all of the essential topics required to achieve the learning objectives.

Training material includes fully indexed course notes creating a complete reference manual.

Content


Day 1


  • Introduction to Arm Architecture
  • Architecture versions • Registers and instruction sets • Exception model • Memory model • Coprocessors • Architecture extensions • The Future
  • Software Engineer's Guide to the CortexTM-R7 MPCore
  • Cortex-R7 MPCore Overview • Operational modes • Level 1 Memory system • Multiprocessing features
  • ISA Overview
  • Load/Store • Data Processing • Flow Control • Misc • DSP
  • Exception Handling
  • Introduction • Interrupts • Abort Handlers • SVC Handlers • Undef • Handlers • Reset Handlers

Day 2


  • Caches and TCMs
  • Cache basics • Caches on Arm processors • Tightly Coupled Memory (TCM) • Optimization considerations
  • Using the Memory Protection Unit
  • Types & AttributesTypes & Attributes • Memory Protection Unit (MPU)
  • Synchronization
  • Introduction to atomicity • Load exclusive and store exclusive instructions • Code examples • Multi-core coherency • Exclusive reservation granule
  • Understanding Barriers
  • Data barriers • Instruction barriers
  • C/C++ Compiler Hints & Tips
  • Basic Compilation • Compiler Optimizations • Coding Considerations • Local and Global Data issues
  • Linker & Libraries Hints & Tips
  • Linking Basics • System and User Libraries • Veneers and Interworking • Linker Optimizations and Diagnostics • Arm Supplied Libraries

Day 3


  • GICv1 & GICv2 Programming
  • Distributor and CPU Interfaces • How to enable and configure interrupts • How to handle interrupts • How to send software interrupts • Security Extensions
  • Further Compiling & Linking Hints & Tips
  • Mixing C/C++ and Assembler • Stack Issues • VFP/NEON • Advanced Building Facilities
  • Embedded Software Development
  • An Out-of-the-box build • Tailoring the C library to your target • Tailoring image memory map to your target • Reset and Initialization • Further memory map considerations • Building and debugging your image
  • Power Management for Cortex-A/R Cores
  • Processor Power Consumption • Power Modes • NEON and MPCore
  • Debug
  • Invasive Debug • Non-Invasive Debug • PMU • Trace

Lab Exercises:


The learning is reinforced with unique Lab exercises using the QEMU virtual platform and covering assembly programming and bringing a complete bare metal system to life. Lab exercises for assembly programming cover the concepts of data transfer, data processing, flow control and DSP instructions, and rely on a combination of GNU compilation tools, GDB and an instruction set simulator used for fast prototyping. Additional exercises show the main steps involved in bringing a bare metal system to life, including the configuration of the various mode stacks and the creation of an interrupt handler. These exercises make use of the assembler and linker as well as the interactive debugger (GDB/CGDB and QEMU).

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