Thursday 17 October 2019

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Arm Cortex-M0+ SoC Design

Standard Level - 2 days

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Arm® Cortex®-M0+ SoC Design is a 2-day class for engineers designing hardware based around the Arm Cortex-M0+ core. The Arm Cortex-M0+ is the smallest Arm core especially designed and optimised for low power applications and has many things in common with the Arm Cortex-M architecture family. This class concentrates on the specific information needed to integrate this core into the System on Chip environment.

The class includes not only an introduction to Arm architecture, Cortex-M0+ programmer's model, AMBA on-chip bus architecture and Cortex-M0+ debug architecture options, it looks in detail at the Cortex-M0+ Power Management architecture and the Interrupt behaviour of this core.

The class includes a number of worked examples developed by Arm to reinforce the lecture material.

Who should attend?

Hardware and system design engineers who need to understand the issues involved when designing SoC's around the Arm Cortex-M0+ core.

Engineers who need to develop and write software can attend our Arm Cortex-M0+ software class.


Some knowledge of embedded systems and familiarity with digital logic and hardware/ASIC design issues. A basic awareness of Arm is useful but not essential.

Training materials

This class uses training materials developed by Arm. Doulos is a global Arm Approved Training Center.


  • Cortex-M0+ Overview
  • Cortex-M0+ Programmer's Model and Instruction Set
  • v6-M Memory Model
  • Interrupt and Exception Handling
  • Cortex-M SysTick timer
  • AHB-Lite
  • Cortex-M System Design Kit
  • Cortex-M0+ Core
  • Cortex-M0+ System Interfaces
  • Cortex-M0+ Memory Protection
  • Cortex-M0+ Integration Example
  • Cortex-M0+ Clocks, Power Management
  • CoreSight System Discovery
  • Cortex-M0+ Debug
  • Cortex-M0+ Trace

Arm and Cortex-M0+ are registered trade marks of Arm Holdings Plc.

Looking for team-based training, or other locations?

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