Standard Level - 5 daysview dates and locations
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Comprehensive VHDL is the industry standard 5-day training course teaching the application of VHDL for FPGA and ASIC design. Fully updated and restructured to reflect current best practice, engineers can attend either the individual modules, or the full 5-day course.
- VHDL for Designers (days 1-3) prepares the engineer for practical project readiness for FPGA designs. While the emphasis is on the practical VHDL-to-hardware flow for FPGA devices, this module also provides the essential foundation needed by ASIC and FPGA designers wishing to apply the more advanced features of VHDL covered in the next module. Delegates targeting FPGAs will take away a flexible project infra-structure which includes a set of scripts, example designs, modules and constraint files to use, adapt and extend on their own projects.
- Advanced VHDL (days 4-5) builds on the foundation of the previous module to prepare the engineer for complex FPGA or ASIC design. It focuses on the use of VHDL for large hierarchical designs, design re-use, and the creation of more powerful test benches.
Workshops comprise approximately 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning.
Doulos is an independent company, enabling delegates to receive the benefit of objective tuition while learning in the context of their chosen tool and methodology. Leading tools supported by this course include:
The course includes specific lab support for tool sets from the leading FPGA vendors including the vendor's native simulation and place-and-route tools.
The tool options available on a specific scheduled course may vary. Preferences can be selected in the booking process. Or please contact Doulos to discuss specific requirements.
Who should attend?
- Engineers who wish to become skilled in the practical use of VHDL for FPGA or ASIC design
- Engineers who are about to embark on the first VHDL design project
- Engineers who have already acquired some practical experience in the use of VHDL, but wish to consolidate and extend their knowledge within a training environment
What will you learn?
VHDL for Designers
- The VHDL language concepts and constructs essential for FPGA design
- How to write VHDL for effective RTL synthesis
- How to target VHDL code to an FPGA device architecture
- How to write simple VHDL test benches
- The tool flow from VHDL through simulation, synthesis and place-and-route
- How to write high quality VHDL code that reflects best practice in the industry
- The VHDL language concepts constructs essential for complex FPGA and ASIC design
- The VHDL language constructs and coding styles that enable sophisticated test benches
- How to code hierarchical designs using multiple VHDL design libraries
- How to write re-usable, parameterisable VHDL code by exploiting generics and data types
- How to run gate-level simulations
Pre-requisitesDelegates must have attended Essential Digital Design Techniques or an equivalent course, or have a good working knowledge of digital hardware design. No previous knowledge of VHDL or a software language is required.
Delegates attending only the Advanced VHDL module must have some hardware design experience, and have completed the VHDL for Designers module or an equivalent course. We have found that delegates frequently overestimate their own capabilities. If in doubt, you will probably benefit from attending the full Comprehensive VHDL course.
Course materialsDoulos Course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world and has made them sought after resources in their own right. Course fees include:
- Fully indexed course notes creating a complete reference manual
- Workbook full of practical examples to help you apply your knowledge
- Doulos Golden Reference Guide for VHDL language, syntax, semantics and tips
- Tool tour guides (to support the tools and technologies of your choice)
- Design flow guide for ASIC and the leading FPGA/CPLD technologies
Structure and Content
VHDL for Designers (days 1-3)
IntroductionThe scope and application of VHDL • Design and tool flow • FPGAs • The VHDL world
Getting StartedThe basic VHDL language constructs • VHDL source files and libraries • The compilation procedure • Synchronous design and timing constraints
FPGA Design Flow (Practical exercises using a hardware board)Simulation • Synthesis • Place-and-Route • Device programming
Design EntitiesEntities and Architectures • Std_logic • Signals and Ports • Concurrent assignments • Instantiation and Port Maps • The Context Clause
ProcessesThe Process statement • Sensitivity list versus Wait • Signal assignments and delta delays • Register transfers • Default assignment • Simple Testbenches
Synthesising Combinational LogicIf statements • Conditional signal assignments and Equivalent process • Transparent latches • Case statements • Synthesis of combinational logic
TypesVHDL types • Standard packages • Integer subtypes • Std_logic and std_logic_vector • Slices and concatenation • Integer and vector values
Synthesis of ArithmeticArithmetic operator overloading • Arithmetic packages • Mixing integers and vectors • Resizing vectors • Resource sharing
Synthesising Sequential LogicRISING_EDGE • Asynchronous set or reset • Synchronous inputs and clock enables • Synthesisable process templates • Implying registers
FSM SynthesisEnumeration types • VHDL coding styles for FSMs • State encoding • Unreachable states and input hazards
MemoriesArray types • Modelling memories • IP Generators • Instantiating generated components • Implementing ROMs
Basic TEXTIOTEXTIO • READ and WRITE • Using TEXTIO for testbench stimulus and outputs • STD_LOGIC_TEXTIO
Advanced VHDL (days 4-5)
More About TypesVariables • Loops • Std_logic and resolution • Array and integer subtypes • Aggregates
Managing Hierarchical DesignsHierarchical design flow • Library name mapping • Component declaration • Configuration • Hierarchical configurations • Compilation order
Parameterised Design EntitiesArray and type attributes • Port Maps • Generics and Generic Maps • Generate statement • Generics and generate
Procedural TestbenchesSubprograms • Procedures • Functions • Parameters and Parameter Association • Package declarations • Package bodies • Subprograms in packages • Subprogram overloading • Operator overloading • Qualified expressions • RTL Procedures
Text-File-Based TestbenchesAssertions • Opening and closing files • Catching TEXTIO errors • Converting between VHDL types and strings • Checking simulation results • Initialising memories • Foreign bodies
Gate Level SimulationRationale for gate level simulation • VITAL tool flow • Reuse of RTL testbench at gate level • Comparison of RTL and gate level results • Behavioural modelling
|October 8th, 2018||Ringwood, UK||Enquire|
|October 15th, 2018||San Jose, CA||Enquire|
|October 22nd, 2018||Columbia, MD||Enquire|
|November 19th, 2018||Munich, DE||Enquire|
|November 19th, 2018||Ringwood, UK||Enquire|
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|January 14th, 2019||Ringwood, UK||Enquire|
|January 21st, 2019||Munich, DE||Enquire|
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|March 25th, 2019||Ringwood, UK||Enquire|
|April 1st, 2019||Copenhagen, DK||Enquire|
|April 1st, 2019||Stockholm, SE||Enquire|
|April 8th, 2019||Munich, DE||Enquire|
|April 29th, 2019||Ringwood, UK||Enquire|
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