Tuesday 22 May 2018

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Xilinx - Designing an Integrated PCI Express System

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Course Description

Attending the Designing an Integrated PCI Express System will provide you a working knowledge of how to implement a Xilinx PCI Express® core in your applications. This course focuses on the implementation of a Xilinx PCI Express system within the Connectivity Targeted Reference Design (TRD). With this experience, you can improve your time to market with your PCIe core design. Various Xilinx PCI Express core products will be enumerated to aid you in selecting the proper solution. This course focuses on the AXI streaming interconnect.

Training Duration

2 days

Who Should Attend?

  • Hardware designers who want to create applications using Xilinx IP cores for PCI Express
  • Software engineers who want to understand the deeper workings of the Xilinx PCI Express solution
  • System architects who want to leverage key Xilinx advantages related to performance, latency, and bandwidth in PCI Express applications

Prerequisites

  • Experience with PCIe specification protocol
  • Knowledge of VHDL or Verilog
  • Some experience with Xilinx implementation tools
  • Some experience with a simulation tool, preferably the Vivado® simulator
  • Moderate digital design experience

Software Tools

  • Xilinx ISE® Design Suite: Logic or System Edition 2013.4

Hardware

  • Architecture: 7 series FPGAs*
  • Demo board: Kintex™-7 FPGA KC705 board*
* This course focuses on the 7 series architecture. Please contact Doulos for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will know how to:
  • Construct a basic PCIe system by:
    • Selecting the appropriate core for your application
    • Specifying requirements of an endpoint application
    • Connecting this endpoint with the core
    • Utilizing FPGA resources to support the core
    • Simulating the design
  • Identify the advanced capabilities of the PCIe specification protocol and feature set

Course Outline

Day 1

  • Course Introduction
  • Introduction to the PCIe Architecture
  • Review of the PCIe Protocol
  • PCIe and the CORE Generator™ Interface
  • Lab 1: Constructing the PCIe Core
  • Simulating a PCIe System Design
  • Connecting Logic to the Core – AXI Interface
  • Packet Formatting Details
  • Lab 2: Downstream Port Model Simulation

Day 2

  • Endpoint Application Considerations
  • Lab 3: Pseudo-Transactional Modeling
  • Application Focus: DMA
  • Lab 4: Design Implementation
  • 7 Series Root Port
  • PCIe Configuration
  • Compliance and Debugging
  • Lab 5: Debugging the PCIe Core with the Vivado Logic Analyzer
  • Errors and Interrupts
  • Course Summary
  • Appendix: Mechanicals, Hot Plug, and Power
  • Appendix: Connecting Logic to the Core - Local Link

Lab Descriptions

  • Lab 1: Constructing the PCIe Core – This lab familiarizes you with the necessary flow for generating a Xilinx Integrated PCI Express Endpoint core from the IP catalog. You will select appropriate parameters and create the PCIe core used throughout the labs.
  • Lab 2: Downstream Port Model Simulation – This lab demonstrates how timing and behavior of a typical link negotiation using the Vivado simulator. You will observe and capture the effects of link training and write packets to the endpoint application for later use.
  • Lab 3: Pseudo-Transactional Modeling – This lab illustrates pseudo-transactional modeling, which provides various packets to the user design without the need to simulate the PCIe cores themselves.
  • Lab 4: Design Implementation – This lab familiarizes you with all the necessary steps and recommended settings to turn the HDL source to a bitstream.
  • Lab 5: Debugging the PCIe Core with the Vivado Logic Analyzer – This lab illustrates how to use the Vivado logic analyzer to monitor the behavior of the core and the endpoint application for proper operation.

Looking for team-based training, or other locations?

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