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Essential Digital Design Techniques

COVID-19: April - June 2020
Training Available Live Online Only - View Now »

Course Dates:
June 29th, 2020 ONLINE EurAsia Enquire
June 29th, 2020 ONLINE Americas Enquire
August 3rd, 2020 ONLINE Americas Enquire
October 5th, 2020 ONLINE EurAsia Enquire
November 2nd, 2020 ONLINE Americas Enquire
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F2F trainingFoundation Level - 2 days

 Auf Deutsch

Essential Digital Design Techniques is a fast-track, application orientated course designed to bridge the gap between text book theory and real world digital design practice.

It significantly accelerates the on-the-job learning curve for engineers new to digital design, or those needing to refine their design skills before project involvement. With a strong emphasis on practical design and hands-on workshops, this course has been specifically developed to capture design techniques usually learned over months, in an intensive 2-day format.

Essential Digital Design Techniques provides the ideal first stage in full scale project training for graduate design engineers, or engineers moving into digital design from other disciplines (including software or analog design). As such, it is the natural precursor to the Doulos Comprehensive VHDL and Comprehensive Verilog courses, which prepare engineers for HDL application within FPGA or ASIC design projects.

Who should attend

  • New graduate engineers embarking on a first project, or engineers with limited practical experience of digital design.
  • Engineers from other disciplines (e.g. software design or analog design) re-training for digital design involvement, or requiring familiarisation with modern digital design techniques.

Pre-requisites

A secondary/high school level understanding of electrical circuits is the only pre-requisite for this training. Delegates require no prior involvement in digital design projects or HDL knowledge.

What you will learn

  • Basic principles of digital logic design and how they are applied to real world applications
  • Combinational and Sequential Logic Design for PLDs and ASICs, with an emphasis on synchronous design techniques
  • How to design and implement fundamental structures e.g. decoders, multiplexers, shift registers, counters
  • How to design and implement synchronous Finite State Machines
  • An overview of ASIC and field programmable logic design, including design practices for state of the art devices
  • Designing with programmable devices
  • Effective Design methodologies and flows, including an introduction to the principles of design using Hardware Description Languages

PLEASE NOTE:
this course does not teach, or require knowledge of a specific Hardware Description Language.

Course Hardware

All hardware is provided for this training. The course includes support for tool sets from the leading FPGA vendors. Please discuss any specific requirements you have during the booking process.

Course materials

Doulos Course materials are renowned for being the most comprehensive and user friendly available. Course Fees include:
  • Fully indexed course notes creating a complete reference manual
  • Workbook full of practical examples and solutions to help you apply your knowledge

Structure and Content

Introduction

  • Representing data using electronics
  • Advantages of digital design over software and analog hardware
  • Basic design flow and software tools
  • Introducing Hardware Description Languages (HDLs)

Digital Design Basics

  • Boolean algebra
  • Combinational logic
  • Implementing logic gates in hardware
  • Asynchronous sequential logic

Synchronous Design

  • Sequential logic, clocks and flip-flops
  • Implementing sequential logic in hardware
  • Timing violations
  • Safe design rules
  • Static timing analysis
  • Types of flip-fop

Digital Design Technologies

  • Application Specific Integrated Circuits (ASICs)
  • Evolution of Programmable Logic Devices
  • Volatile and non-volatile technologies
  • Economic considerations
  • Choosing between different technologies and devices

Design Practices

  • Representing combinational logic in HDLs
  • Representing sequential logic in HDLs
  • Resource sharing
  • Scalable design
  • Design trade-offs
  • Introducing verification

Common Functions

  • Encoders and decoders
  • Priority encoders
  • Multiplexers
  • Parity generator
  • Shift Registers
  • Johnson (ring) "counters"
  • Linear Feedback Shift Registers

Arithmetic Structures

  • Unsigned and two's complement arithmetic
  • Half and full adders
  • Large adders
  • Carry lookahead adder
  • Pipelining
  • Synthesis of adders
  • Counters
  • Wide counters
  • Binary to BCD conversion
  • Serial arithmetic

Outside the Synchronous World

  • Representing digital logic using analog components
  • Inputs hazards and metastability
  • Three-state buses
  • Pin locking
  • Working safely with clocks and resets
  • I/O buffers and I/O standards
  • Ground bounce, termination and other analog issues

Finite State Machines and IP Blocks

Price on request


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